Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/frv/lddc.cgs
2023-03-06 14:48:14 +01:00

45 lines
1 KiB
Text

# frv testcase for lddc @($GRi,$GRj),$GRk
# mach: frv
# as(frv): -mcpu=frv
.include "testutils.inc"
start
.global lddc
lddc:
set_mem_limmed 0xdead,0xbeef,sp
inc_gr_immed -4,sp
set_mem_limmed 0xbeef,0xdead,sp
set_cpr_limmed 0xdead,0xbeef,cpr8
set_cpr_limmed 0xbeef,0xdead,cpr9
set_gr_immed 0,gr7
; loading into cpr0 is business as usual
set_cpr_limmed 0xdead,0xbeef,cpr0
set_cpr_limmed 0xbeef,0xdead,cpr1
lddc @(sp,gr7),cpr0
test_cpr_limmed 0xbeef,0xdead,cpr0
test_cpr_limmed 0xdead,0xbeef,cpr1
lddc @(sp,gr7),cpr8
test_cpr_limmed 0xbeef,0xdead,cpr8
test_cpr_limmed 0xdead,0xbeef,cpr9
set_cpr_limmed 0xdead,0xbeef,cpr8
set_cpr_limmed 0xbeef,0xdead,cpr9
inc_gr_immed -8,sp
set_gr_immed 8,gr7
lddc @(sp,gr7),cpr8
test_cpr_limmed 0xbeef,0xdead,cpr8
test_cpr_limmed 0xdead,0xbeef,cpr9
set_cpr_limmed 0xdead,0xbeef,cpr8
set_cpr_limmed 0xbeef,0xdead,cpr9
inc_gr_immed 16,sp
set_gr_immed -8,gr7
lddc @(sp,gr7),cpr8
test_cpr_limmed 0xbeef,0xdead,cpr8
test_cpr_limmed 0xdead,0xbeef,cpr9
pass