Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/frv/fbuglr.cgs
2023-03-06 14:48:14 +01:00

88 lines
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# frv testcase for fbuglr $FCCi,$hint
# mach: all
.include "testutils.inc"
start
.global fbuglr
fbuglr:
set_spr_addr bad,lr
set_fcc 0x0 0
fbuglr fcc0,0
set_spr_addr ok2,lr
set_fcc 0x1 1
fbuglr fcc1,1
fail
ok2:
set_spr_addr ok3,lr
set_fcc 0x2 2
fbuglr fcc2,2
fail
ok3:
set_spr_addr ok4,lr
set_fcc 0x3 3
fbuglr fcc3,3
fail
ok4:
set_spr_addr bad,lr
set_fcc 0x4 0
fbuglr fcc0,0
set_spr_addr ok6,lr
set_fcc 0x5 1
fbuglr fcc1,1
fail
ok6:
set_spr_addr ok7,lr
set_fcc 0x6 2
fbuglr fcc2,2
fail
ok7:
set_spr_addr ok8,lr
set_fcc 0x7 3
fbuglr fcc3,3
fail
ok8:
set_spr_addr bad,lr
set_fcc 0x8 0
fbuglr fcc0,0
set_spr_addr oka,lr
set_fcc 0x9 1
fbuglr fcc1,1
fail
oka:
set_spr_addr okb,lr
set_fcc 0xa 2
fbuglr fcc2,2
fail
okb:
set_spr_addr okc,lr
set_fcc 0xb 3
fbuglr fcc3,3
fail
okc:
set_spr_addr bad,lr
set_fcc 0xc 0
fbuglr fcc0,0
set_spr_addr oke,lr
set_fcc 0xd 1
fbuglr fcc1,1
fail
oke:
set_spr_addr okf,lr
set_fcc 0xe 2
fbuglr fcc2,2
fail
okf:
set_spr_addr okg,lr
set_fcc 0xf 3
fbuglr fcc3,3
fail
okg:
pass
bad:
fail