Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/d10v/t-rte.s
2023-03-06 14:48:14 +01:00

22 lines
252 B
ArmAsm

# mach: all
# output:
# sim: --environment operating
.include "t-macros.i"
start
PSW_BITS = PSW_C|PSW_F0|PSW_F1
ldi r6, #success@word
mvtc r6, bpc
ldi r6, #PSW_BITS
mvtc r6, bpsw
test_rte:
RTE
exit47
success:
checkpsw2 1 PSW_BITS
exit0