235 lines
3 KiB
OpenEdge ABL
235 lines
3 KiB
OpenEdge ABL
# mach: d10v
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# output:
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# sim: --environment operating
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.macro start
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.text
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.align 2
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.globl _start
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_start:
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ldi r0, 0
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.endm
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.macro exit47
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ldi r4, 1
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ldi r0, 47
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trap 15
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.endm
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.macro exit0
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ldi r4, 1
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ldi r0, 0
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trap 15
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.endm
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.macro exit1
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ldi r4, 1
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ldi r0, 1
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trap 15
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.endm
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.macro exit2
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ldi r4, 1
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ldi r0, 2
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trap 15
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.endm
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.macro load reg val
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ldi \reg, #\val
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.endm
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.macro load2w reg hi lo
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ld2w \reg, @(1f,r0)
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.data
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.align 2
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1: .short \hi
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.short \lo
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.text
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.endm
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.macro check exit reg val
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cmpeqi \reg, #\val
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brf0t 1f
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0: ldi r4, 1
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ldi r0, \exit
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trap 15
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1:
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.endm
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.macro check2w2 exit reg hi lo
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st2w \reg, @(1f,r0)
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ld r2, @(1f, r0)
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cmpeqi r2, #\hi
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brf0f 0f
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ld r2, @(1f + 2, r0)
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cmpeqi r2, #\lo
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brf0f 0f
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bra 2f
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0: ldi r4, 1
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ldi r0, \exit
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trap 15
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.data
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.align 2
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1: .long 0
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.text
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2:
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.endm
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.macro loadacc2 acc guard hi lo
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ldi r2, #\lo
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mvtaclo r2, \acc
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ldi r2, #\hi
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mvtachi r2, \acc
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ldi r2, #\guard
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mvtacg r2, \acc
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.endm
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.macro checkacc2 exit acc guard hi lo
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ldi r2, #\guard
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mvfacg r3, \acc
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cmpeq r2, r3
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brf0f 0f
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ldi r2, #\hi
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mvfachi r3, \acc
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cmpeq r2, r3
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brf0f 0f
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ldi r2, #\lo
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mvfaclo r3, \acc
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cmpeq r2, r3
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brf0f 0f
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bra 4f
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0: ldi r4, 1
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ldi r0, \exit
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trap 15
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4:
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.endm
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.macro loadpsw2 val
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ldi r2, #\val
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mvtc r2, cr0
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.endm
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.macro checkpsw2 exit val
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mvfc r2, cr0
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cmpeqi r2, #\val
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brf0t 1f
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ldi r4, 1
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ldi r0, \exit
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trap 15
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1:
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.endm
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.macro hello
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;; 4:write (1, string, strlen (string))
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ldi r4, 4
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ldi r0, 1
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ldi r1, 1f
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ldi r2, 2f-1f-1
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trap 15
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.section .rodata
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1: .string "Hello World!\n"
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2: .align 2
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.text
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.endm
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;;; Blat our DMAP registers so that they point at on-chip imem
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.macro point_dmap_at_imem
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.text
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ldi r2, MAP_INSN | 0xf
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st r2, @(DMAP_REG,r0)
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ldi r2, MAP_INSN
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st r2, @(IMAP1_REG,r0)
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.endm
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;;; Patch VEC so that it jumps back to code that checks PSW
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;;; and then exits with success.
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.macro check_interrupt vec psw src
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;;; Patch the interrupt vector's AE entry with a jmp to success
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.text
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ldi r4, #1f
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ldi r5, \vec
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;;
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ld2w r2, @(0,r4)
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st2w r2, @(0,r5)
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ld2w r2, @(4,r4)
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st2w r2, @(4,r5)
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;;
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bra 9f
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nop
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;;; Code that gets patched into the interrupt vector
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.data
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1: ldi r1, 2f@word
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jmp r1
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;;; Successfull trap jumps back to here
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.text
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;;; Verify the PSW
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2: mvfc r2, cr0
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cmpeqi r2, #\psw
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brf0t 3f
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nop
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exit1
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;;; Verify the original addr
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3: mvfc r2, bpc
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cmpeqi r2, #\src@word
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brf0t 4f
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exit2
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4: exit0
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;;; continue as normal
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9:
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.endm
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PSW_SM = 0x8000
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PSW_01 = 0x4000
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PSW_EA = 0x2000
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PSW_DB = 0x1000
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PSW_DM = 0x0800
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PSW_IE = 0x0400
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PSW_RP = 0x0200
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PSW_MD = 0x0100
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PSW_FX = 0x0080
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PSW_ST = 0x0040
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PSW_10 = 0x0020
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PSW_11 = 0x0010
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PSW_F0 = 0x0008
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PSW_F1 = 0x0004
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PSW_14 = 0x0002
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PSW_C = 0x0001
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;;;
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DMAP_MASK = 0x3fff
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DMAP_BASE = 0x8000
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DMAP_REG = 0xff04
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IMAP0_REG = 0xff00
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IMAP1_REG = 0xff02
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MAP_INSN = 0x1000
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;;;
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VEC_RI = 0x3ff00
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VEC_BAE = 0x3ff04
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VEC_RIE = 0x3ff08
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VEC_AE = 0x3ff0c
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VEC_TRAP = 0x3ff10
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VEC_DBT = 0x3ff50
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VEC_SDBT = 0x3fff4
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VEC_DBI = 0x3ff58
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VEC_EI = 0x3ff5c
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