239 lines
4 KiB
ArmAsm
239 lines
4 KiB
ArmAsm
# Blackfin testcase for register load instructions
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# mach: bfin
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.include "testutils.inc"
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start
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.macro load32 num:req, reg0:req, reg1:req
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imm32 \reg0 \num
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imm32 \reg1 \num
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CC = \reg0 == \reg1
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if CC jump 2f;
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fail
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2:
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.endm
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.macro load32p num:req preg:req
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imm32 r0 \num
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imm32 \preg \num
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r1 = \preg
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cc = r0 == r1
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if CC jump 3f;
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fail
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3:
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imm32 \preg 0
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.endm
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.macro load16z num:req reg0:req reg1:req
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\reg0 = \num (Z);
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imm32 \reg1 \num
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CC = \reg0 == \reg1
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if CC jump 4f;
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fail
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4:
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.endm
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.macro load16zp num:req reg:req
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\reg = \num (Z);
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imm32 r1 \num;
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r0 = \reg;
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cc = r0 == r1
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if CC jump 5f;
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fail
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5:
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.endm
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.macro load16x num:req reg0:req reg1:req
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\reg0 = \num (X);
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imm32 \reg1, \num
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CC = \reg0 == \reg1
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if CC jump 6f;
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fail
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6:
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.endm
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/* Clobbers R0 */
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.macro loadinc preg0:req, preg1:req, dreg:req
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loadsym \preg0, _buf
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\preg1 = \preg0;
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\dreg = \preg0;
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[\preg0\()++] = \preg0;
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\dreg += 4;
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R0 = \preg0;
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CC = \dreg == R0;
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if CC jump 7f;
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fail
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7:
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R0 = [ \preg1\() ];
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\dreg += -4;
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CC = \dreg == R0;
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if CC jump 8f;
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fail
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8:
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.endm
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/* test a bunch of values */
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/* load_immediate (Half-Word Load)
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* register = constant
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* reg_lo = uimm16;
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* reg_hi = uimm16;
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*/
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load32 0 R0 R1
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load32 0xFFFFFFFF R0 R1
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load32 0x55aaaa55 r0 r1
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load32 0x12345678 r0 r1
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load32 0x12345678 R0 R2
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load32 0x23456789 R0 R3
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load32 0x3456789a R0 R4
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load32 0x456789ab R0 R5
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load32 0x56789abc R0 R6
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load32 0x6789abcd R0 R7
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load32 0x789abcde R0 R0
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load32 0x89abcdef R1 R0
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load32 0x9abcdef0 R2 R0
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load32 0xabcdef01 R3 R0
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load32 0xbcdef012 R4 R0
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load32 0xcdef0123 R5 R0
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load32 0xdef01234 R6 R0
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load32 0xef012345 R7 R0
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load32p 0xf0123456 P0
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load32p 0x01234567 P1
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load32p 0x12345678 P2
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.ifndef BFIN_HOST
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load32p 0x23456789 P3
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.endif
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load32p 0x3456789a P4
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load32p 0x456789ab P5
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load32p 0x56789abc SP
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load32p 0x6789abcd FP
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load32p 0x789abcde I0
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load32p 0x89abcdef I1
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load32p 0x9abcdef0 I2
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load32p 0xabcdef01 I3
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load32p 0xbcdef012 M0
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load32p 0xcdef0123 M1
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load32p 0xdef01234 M2
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load32p 0xef012345 M3
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load32p 0xf0123456 B0
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load32p 0x01234567 B1
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load32p 0x12345678 B2
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load32p 0x23456789 B3
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load32p 0x3456789a L0
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load32p 0x456789ab L1
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load32p 0x56789abc L2
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load32p 0x6789abcd L3
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/* Zero Extended */
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load16z 0x1234 R0 R1
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load16z 0x2345 R0 R1
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load16z 0x3456 R0 R2
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load16z 0x4567 R0 R3
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load16z 0x5678 R0 R4
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load16z 0x6789 R0 R5
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load16z 0x789a R0 R6
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load16z 0x89ab R0 R7
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load16z 0x9abc R1 R0
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load16z 0xabcd R2 R0
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load16z 0xbcde R3 R0
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load16z 0xcdef R4 R0
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load16z 0xdef0 R5 R0
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load16z 0xef01 R6 R0
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load16z 0xf012 R7 R0
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load16zp 0x0123 P0
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load16zp 0x1234 P1
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load16zp 0x1234 p2
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.ifndef BFIN_HOST
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load16zp 0x2345 p3
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.endif
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load16zp 0x3456 p4
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load16zp 0x4567 p5
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load16zp 0x5678 sp
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load16zp 0x6789 fp
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load16zp 0x789a i0
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load16zp 0x89ab i1
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load16zp 0x9abc i2
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load16zp 0xabcd i3
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load16zp 0xbcde m0
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load16zp 0xcdef m1
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load16zp 0xdef0 m2
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load16zp 0xef01 m3
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load16zp 0xf012 b0
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load16zp 0x0123 b1
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load16zp 0x1234 b2
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load16zp 0x2345 b3
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load16zp 0x3456 l0
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load16zp 0x4567 l1
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load16zp 0x5678 l2
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load16zp 0x6789 l3
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/* Sign Extended */
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load16x 0x20 R0 R1
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load16x 0x3F R0 R1
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load16x -0x20 R0 R1
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load16x -0x3F R0 R1
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load16x 0x1234 R0 R1
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load16x 0x2345 R0 R1
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load16x 0x3456 R0 R2
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load16x 0x4567 R0 R3
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load16x 0x5678 R0 R4
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load16x 0x6789 R0 R5
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load16x 0x789a R0 R6
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load16x 0x09ab R0 R7
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load16x -0x1abc R1 R0
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load16x -0x2bcd R2 R0
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load16x -0x3cde R3 R0
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load16x -0x4def R4 R0
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load16x -0x5ef0 R5 R0
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load16x -0x6f01 R6 R0
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load16x -0x7012 R7 R0
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loadinc P0, P1, R1
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loadinc P1, P2, R1
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loadinc P2, P1, R2
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.ifndef BFIN_HOST
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loadinc P3, P4, R3
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.endif
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loadinc P4, P5, R4
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loadinc FP, P0, R7
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loadinc P0, I0, R1
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loadinc P1, I1, R1
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loadinc P2, I2, R1
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.ifndef BFIN_HOST
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loadinc P3, I0, R1
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.endif
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loadinc P4, I2, R1
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loadinc P5, I3, R1
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A1 = A0 = 0;
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R0 = 0x01 (Z);
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A0.x = R0;
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imm32 r4, 0x32e02d1a
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A1.x = R4;
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A0.w = A1.x;
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R3 = A0.w;
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R2 = A0.x;
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imm32 r0, 0x0000001a
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imm32 r1, 0x00000001
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CC = R1 == R2;
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if CC jump 1f;
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fail
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1:
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CC = R0 == R3
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if CC jump 2f;
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fail
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2:
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pass
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.data
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_buf:
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.rept 0x80
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.long 0
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.endr
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