129 lines
2 KiB
ArmAsm
129 lines
2 KiB
ArmAsm
# Blackfin testcase for branching out of the middle of a hardware loop
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# mach: bfin
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.include "testutils.inc"
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.macro test_prep lc:req, sym:req
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imm32 P0, \lc
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loadsym P1, \sym
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R5 = 0;
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R6 = 0;
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R7 = 0;
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LSETUP (1f, 2f) LC0 = P0;
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.endm
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.macro test_check exp5:req, exp6:req, exp7:req, expLC
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imm32 R4, \exp5;
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CC = R4 == R5;
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IF !CC JUMP 2f;
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imm32 R4, \exp6;
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CC = R4 == R6;
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IF !CC JUMP 2f;
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imm32 R4, \exp7;
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CC = R4 == R7;
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IF !CC JUMP 2f;
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R3 = LC0;
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imm32 R4, \expLC;
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CC = R4 == R3;
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IF !CC JUMP 2f;
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JUMP 3f;
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2: fail
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3:
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.endm
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start
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mnop;
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test_jump_s:
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.macro test_jump_s lc:req
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test_prep \lc, 3f
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1: JUMP (P1);
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R5 += 1;
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2: R6 += 1;
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fail
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3: R7 += 1;
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test_check 0, 0, 1, \lc
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.endm
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test_jump_s 0
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test_jump_s 1
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test_jump_s 2
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test_jump_s 10
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test_jump_m:
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.macro test_jump_m lc:req
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test_prep \lc, 3f
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1: R5 += 1;
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JUMP (P1);
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2: R6 += 1;
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fail
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3: R7 += 1;
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test_check 1, 0, 1, \lc
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.endm
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test_jump_m 0
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test_jump_m 1
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test_jump_m 2
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test_jump_m 10
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test_jump_e:
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.macro test_jump_e lc:req, lcend:req
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test_prep \lc, 3f
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1: R5 += 1;
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R6 += 1;
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2: JUMP (P1);
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fail
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3: R7 += 1;
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test_check 1, 1, 1, \lcend
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.endm
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test_jump_e 0, 0
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test_jump_e 1, 0
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test_jump_e 2, 1
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test_jump_e 10, 9
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test_call_s:
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.macro test_call_s lc:req, exp5:req, exp6:req, exp7:req
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test_prep \lc, __ret
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1: CALL (P1);
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R5 += 1;
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2: R6 += 1;
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3: R7 += 1;
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test_check \exp5, \exp6, \exp7, 0
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.endm
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test_call_s 0, 1, 1, 2
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test_call_s 1, 1, 1, 2
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test_call_s 2, 2, 2, 3
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test_call_s 10, 10, 10, 11
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test_call_m:
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.macro test_call_m lc:req, exp5:req, exp6:req, exp7:req
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test_prep \lc, __ret
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1: R5 += 1;
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CALL (P1);
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2: R6 += 1;
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3: R7 += 1;
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test_check \exp5, \exp6, \exp7, 0
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.endm
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test_call_m 0, 1, 1, 2
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test_call_m 1, 1, 1, 2
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test_call_m 2, 2, 2, 3
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test_call_m 10, 10, 10, 11
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test_call_e:
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.macro test_call_e lc:req, exp5:req, exp6:req, exp7:req
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test_prep \lc, __ret
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1: R5 += 1;
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R6 += 1;
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2: CALL (P1);
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3: R7 += 1;
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test_check \exp5, \exp6, \exp7, 0
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.endm
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test_call_e 0, 1, 1, 2
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test_call_e 1, 1, 1, 2
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test_call_e 2, 2, 2, 3
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test_call_e 10, 10, 10, 11
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pass
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__ret:
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nop;nop;nop;
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R7 += 1;
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rts;
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