122 lines
2 KiB
ArmAsm
122 lines
2 KiB
ArmAsm
# Blackfin testcase for having RETI LSB set correctly when self nested
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# mach: bfin
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# sim: --environment operating
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#include "test.h"
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.include "testutils.inc"
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start
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# Set our handler
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imm32 P5, EVT11;
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loadsym R1, _ivg11;
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[P5] = R1;
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loadsym R1, _fail_lvl;
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[P5 + 4] = R1; /* IVG12 */
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[P5 + 12] = R1; /* IVG14 */
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loadsym R1, _ivg13;
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[P5 + 8] = R1;
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# Enable self nesting
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R2 = SYSCFG;
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BITSET (R2, 2);
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SYSCFG = R2;
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CSYNC;
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# Enable IVG11/IVG13/IVG14 but not IVG12
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cli R3;
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BITSET (R3, 11);
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BITCLR (R3, 12);
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BITSET (R3, 13);
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BITSET (R3, 14);
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sti R3;
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# Counter to keep track of nesting depth
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R7 = 0;
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# Lower ourselves to IVG11
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loadsym R4, _fail_lvl;
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RETI = R4;
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RAISE 11;
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RAISE 12;
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RAISE 13;
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RAISE 14;
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RTI;
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# This IVG makes sure RETI LSB is set correctly on transition in (RAISE)
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_ivg11:
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R0 = RETI;
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# Make sure we are indeed at IVG11
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imm32 P0, IPEND;
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R1 = [P0];
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CC = BITTST (R1, 11);
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IF !CC JUMP _fail_lvl;
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# Make sure LSB of RETI is set only on first pass
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CC = ! BITTST (R0, 0);
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R1 = CC;
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CC = R7 == 0;
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R2 = CC;
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CC = R1 == R2;
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IF !CC JUMP _fail_lvl;
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# Nest ourselves a few times
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R6 = 3;
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CC = R7 < R6;
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IF !CC JUMP 1f;
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[--sp] = RETI;
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R7 += 1;
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RAISE 11;
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MNOP;
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JUMP _fail_lvl;
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# Move down to IVG13 for next test
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1: loadsym R4, _fail_lvl;
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RETI = R4;
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RTI;
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# This IVG makes sure RETI LSB is respected on transition out (RTI)
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_ivg13:
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R0 = RETI;
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# Make sure we are indeed at IVG13
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imm32 P0, IPEND;
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R1 = [P0];
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CC = BITTST (R1, 13);
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IF !CC JUMP _fail_lvl;
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# RETI LSB should be set when re-entering IVG13
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CC = ! BITTST (R0, 0);
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R1 = CC;
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CC = R7 == R6;
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R2 = CC;
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CC = R1 == R2;
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IF !CC JUMP _fail_lvl;
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# Should get here only after a few IVG11 tests
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CC = R7 < R6;
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IF CC JUMP _fail_lvl;
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# Make sure IVG13 isn't pending
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imm32 P0, ILAT;
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R1 = [P0];
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CC = BITTST (R1, 13);
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IF CC JUMP _fail_lvl;
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# Manually set RETI to with LSB set so we return there
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R5 = R6;
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R5 += 3;
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CC = R7 < R5;
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IF !CC JUMP 1f;
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loadsym R1, _ivg13;
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BITSET (R1, 0);
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RETI = R1;
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R7 += 1;
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RTI;
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# All done!
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1: dbg_pass
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_fail_lvl:
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dbg_fail;
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