171 lines
2.6 KiB
ArmAsm
171 lines
2.6 KiB
ArmAsm
# mach: aarch64
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# Check the store multiple structure instructions: st1, st2, st3, st4.
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# Check the addressing modes: no offset, post-index immediate offset,
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# post-index register offset.
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.include "testutils.inc"
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.data
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.align 4
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input:
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.word 0x04030201
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.word 0x08070605
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.word 0x0c0b0a09
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.word 0x100f0e0d
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.word 0xfcfdfeff
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.word 0xf8f9fafb
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.word 0xf4f5f6f7
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.word 0xf0f1f2f3
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output:
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.zero 64
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start
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adrp x0, input
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add x0, x0, :lo12:input
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adrp x1, output
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add x1, x1, :lo12:output
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mov x2, x0
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ldr q0, [x2], 16
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ldr q1, [x2]
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mov x2, x0
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ldr q2, [x2], 16
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ldr q3, [x2]
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mov x2, x1
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mov x3, #16
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st1 {v0.16b}, [x2], 16
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st1 {v1.8h}, [x2], x3
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mov x2, x1
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ldr q4, [x2], 16
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ldr q5, [x2]
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addv b4, v4.16b
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addv b5, v5.16b
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mov x4, v4.d[0]
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cmp x4, #136
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bne .Lfailure
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mov x5, v5.d[0]
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cmp x5, #120
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bne .Lfailure
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mov x2, x1
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mov x3, #16
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st2 {v0.8b, v1.8b}, [x2], 16
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st2 {v2.4h, v3.4h}, [x2], x3
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mov x2, x1
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ldr q4, [x2], 16
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ldr q5, [x2]
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addv b4, v4.16b
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addv b5, v5.16b
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mov x4, v4.d[0]
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cmp x4, #0
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bne .Lfailure
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mov x5, v5.d[0]
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cmp x5, #0
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bne .Lfailure
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mov x2, x1
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st3 {v0.4s, v1.4s, v2.4s}, [x2]
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ldr q4, [x2], 16
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ldr q5, [x2], 16
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ldr q6, [x2]
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addv b4, v4.16b
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addv b5, v5.16b
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addv b6, v6.16b
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mov x4, v4.d[0]
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cmp x4, #36
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bne .Lfailure
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mov x5, v5.d[0]
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cmp x5, #0
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bne .Lfailure
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mov x6, v6.d[0]
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cmp x6, #100
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bne .Lfailure
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mov x2, x1
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st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2]
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ldr q4, [x2], 16
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ldr q5, [x2], 16
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ldr q6, [x2], 16
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ldr q7, [x2]
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addv b4, v4.16b
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addv b5, v5.16b
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addv b6, v6.16b
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addv b7, v7.16b
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mov x4, v4.d[0]
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cmp x4, #0
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bne .Lfailure
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mov x5, v5.d[0]
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cmp x5, #0
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bne .Lfailure
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mov x6, v6.d[0]
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cmp x6, #0
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bne .Lfailure
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mov x7, v7.d[0]
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cmp x7, #0
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bne .Lfailure
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pass
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mov x2, x1
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st1 {v0.2s, v1.2s}, [x2], 16
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st1 {v2.1d, v3.1d}, [x2]
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mov x2, x1
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ldr q4, [x2], 16
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ldr q5, [x2]
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addv b4, v4.16b
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addv b5, v5.16b
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mov x4, v4.d[0]
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cmp x4, #0
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bne .Lfailure
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mov x5, v5.d[0]
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cmp x5, #0
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bne .Lfailure
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mov x2, x1
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st1 {v0.2d, v1.2d, v2.2d}, [x2]
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mov x2, x1
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ldr q4, [x2], 16
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ldr q5, [x2], 16
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ldr q6, [x2]
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addv b4, v4.16b
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addv b5, v5.16b
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addv b6, v6.16b
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mov x4, v4.d[0]
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cmp x4, #136
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bne .Lfailure
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mov x5, v5.d[0]
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cmp x5, #120
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bne .Lfailure
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mov x6, v6.d[0]
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cmp x6, #136
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bne .Lfailure
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mov x2, x1
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st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x2]
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mov x2, x1
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ldr q4, [x2], 16
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ldr q5, [x2], 16
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ldr q6, [x2], 16
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ldr q7, [x2]
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addv b4, v4.16b
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addv b5, v5.16b
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addv b6, v6.16b
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addv b7, v7.16b
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mov x4, v4.d[0]
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cmp x4, #136
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bne .Lfailure
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mov x5, v5.d[0]
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cmp x5, #120
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bne .Lfailure
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mov x6, v6.d[0]
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cmp x6, #136
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bne .Lfailure
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mov x7, v7.d[0]
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cmp x7, #120
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bne .Lfailure
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pass
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.Lfailure:
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fail
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