107 lines
3.5 KiB
Text
107 lines
3.5 KiB
Text
SIM port for the OpenRISC architecture
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Authors: Stafford Horne <shorne@gmail.com>
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Peter Gavin
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# Guide to Code #
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We have tried to comment on the functions in the simulator implementation as
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best as we can. Here we provide some general architecture comments for
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reference. Please let me know if there is a better place for these kind of
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docs.
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The or1k sim uses the CGEN system to generate most of the simulator code. There
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is some documentation for CGEN on sourceware.org here:
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https://sourceware.org/cgen/docs/cgen.html
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In the binutils-gdb project there are several files which get combined to make
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up the CGEN simulator. The process for how those are built can be seen in
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`or1k/Makefile.in`. But the main files are:
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MAIN
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sim/common/nrun.c - the main() calls sim_open(), sim_resume() and others
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sim/or1k/sim-if.c - implements sim_open() and others used by nrun
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when envoking sim in gdb, gdb uses sim_open() directly
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CGEN input and generated files
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cpu/or1k*.cpu - these define the hardware, model and semantics
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sim/or1k/arch.c - generated defines sim_machs array
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sim/or1k/cpu.c - *generated defines register setters and getters
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sim/or1k/decode.c - generated defines instruction decoder
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sim/or1k/model.c - generated defines instruction cycles
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sim/or1k/sem.c - *generated defines instruction operation semantics
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sim/or1k/sem-switch.c - *generated ditto but as a switch
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ENGINE runs decode execute loop
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sim/common/cgen-* - cgen implementation helpers
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sim/common/cgen-run.c - implements sim_resume() which runs the engine
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sim/common/genmloop.sh - helper script to generate mloop.c engine the
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decode, execute loop
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sim/or1k/mloop.in - openRISC implementation of mloop parts
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EXTRAS callbacks from sem* to c code
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sim/or1k/or1k.c - implements some instructions in c (not cgen schema)
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sim/or1k/traps.c - exception handler
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For each sim architecture we have choices for how the mloop is implemented. The
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OpenRISC engine uses scache pbb (pseudo-basic-block) instruction extraction with
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both fast (sem-switch.c based) and full (sem.c based) implementations. The fast
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and full modes are switch via the command line options to the `run` command,
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i.e. --trace-insn will run in full mode.
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# Building #
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Below are some details on how we build and test the openrisc sim.
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## TOOLCHAIN ##
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This may not be needed as binutils contains most/all of the utilities required.
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But if needed, get this toolchain (this is the newlib binary, others also
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available)
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https://github.com/openrisc/or1k-gcc/releases/download/or1k-5.4.0-20170218/or1k-elf-5.4.0-20170218.tar.xz
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If you want to build that from scratch look to:
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https://github.com/openrisc/newlib/blob/scripts/build.sh
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## GDB ##
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In a directory along side binutils-gdb source
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mkdir build-or1k-elf-gdb
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cd build-or1k-elf-gdb
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../binutils-gdb/configure --target=or1k-elf \
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--prefix=/opt/shorne/software/or1k \
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--disable-itcl \
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--disable-tk \
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--disable-tcl \
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--disable-winsup \
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--disable-gdbtk \
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--disable-libgui \
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--disable-rda \
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--disable-sid \
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--with-sysroot \
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--disable-newlib \
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--disable-libgloss \
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--disable-gas \
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--disable-ld \
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--disable-binutils \
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--disable-gprof \
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--with-system-zlib
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# make gdb, sim
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make
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# test sim
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cd sim
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make check
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The sim creates a binary simulator too, you can run binaries such as hello
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world with:
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or1k-elf-gcc hello.c
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./or1k/run --trace-insn ./a.out
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