666 lines
21 KiB
Text
666 lines
21 KiB
Text
2021-06-22 Mike Frysinger <vapier@gentoo.org>
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* configure.ac: Removed.
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* aclocal.m4: Removed.
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* configure: Removed.
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2021-06-21 Mike Frysinger <vapier@gentoo.org>
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* aclocal.m4: Regenerate.
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* configure: Regenerate.
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2021-06-21 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-06-20 Mike Frysinger <vapier@gentoo.org>
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* configure.ac (SIM_AC_COMMON): Delete.
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* aclocal.m4, configure: Regenerate.
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2021-06-20 Mike Frysinger <vapier@gentoo.org>
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* aclocal.m4: Regenerate.
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* configure: Regenerate.
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2021-06-19 Mike Frysinger <vapier@gentoo.org>
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* aclocal.m4: Regenerate.
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* configure: Regenerate.
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2021-06-19 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-06-18 Mike Frysinger <vapier@gentoo.org>
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* aclocal.m4, configure: Regenerate.
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2021-06-18 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-06-18 Mike Frysinger <vapier@gentoo.org>
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* cpustate.c: Include sim-signal.h.
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* memory.c, simulator.c: Likewise.
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2021-06-17 Mike Frysinger <vapier@gentoo.org>
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* configure.ac: Delete SIM_AC_OPTION_ENDIAN call.
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* aclocal.m4, configure: Regenerate.
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2021-06-16 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-06-16 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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* config.in: Removed.
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2021-06-15 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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2021-06-14 Mike Frysinger <vapier@gentoo.org>
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* configure.ac: Delete call to SIM_AC_OPTION_WARNINGS.
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* configure: Regenerate.
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2021-06-12 Mike Frysinger <vapier@gentoo.org>
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* configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT.
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* interp.c (sim_open): Set current_alignment.
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2021-06-12 Mike Frysinger <vapier@gentoo.org>
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* aclocal.m4, config.in, configure: Regenerate.
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2021-06-12 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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2021-05-17 Mike Frysinger <vapier@gentoo.org>
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* sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete.
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2021-05-17 Mike Frysinger <vapier@gentoo.org>
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* sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
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(struct sim_state): Delete.
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2021-05-16 Mike Frysinger <vapier@gentoo.org>
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* cpustate.c: Include defs.h.
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* interp.c: Replace config.h include with defs.h.
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* memory.c, simulator.c: Likewise.
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* cpustate.h, simulator.h: Delete config.h include.
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2021-05-16 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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2021-05-14 Mike Frysinger <vapier@gentoo.org>
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* cpustate.h: Update include path.
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* interp.c: Likewise.
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2021-05-04 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-05-01 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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2021-05-01 Mike Frysinger <vapier@gentoo.org>
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* cpustate.c (aarch64_set_FP_float): Change lx to PRIx64.
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(aarch64_set_FP_double, aarch64_set_FP_long_double,
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aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise.
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2021-05-01 Mike Frysinger <vapier@gentoo.org>
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* simulator.c (do_fcvtzu): Change UL to ULL.
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2021-04-26 Mike Frysinger <vapier@gentoo.org>
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* aclocal.m4, config.in, configure: Regenerate.
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2021-04-22 Tom Tromey <tom@tromey.com>
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* configure, config.in: Rebuild.
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2021-04-22 Tom Tromey <tom@tromey.com>
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* configure: Rebuild.
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2021-04-21 Mike Frysinger <vapier@gentoo.org>
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* aclocal.m4: Regenerate.
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2021-04-21 Simon Marchi <simon.marchi@polymtl.ca>
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* configure: Regenerate.
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2021-04-18 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-04-12 Mike Frysinger <vapier@gentoo.org>
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* interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all.
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2021-04-07 Jim Wilson <jimw@sifive.com>
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PR sim/27483
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* simulator.c (set_flags_for_add32): Compare uresult against
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itself. Compare sresult against itself.
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2021-04-02 Mike Frysinger <vapier@gentoo.org>
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* aclocal.m4, configure: Regenerate.
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2021-02-28 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-02-21 Mike Frysinger <vapier@gentoo.org>
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* configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4.
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* aclocal.m4, configure: Regenerate.
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2021-02-13 Mike Frysinger <vapier@gentoo.org>
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* configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS.
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* aclocal.m4, configure: Regenerate.
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2021-02-06 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-01-11 Mike Frysinger <vapier@gentoo.org>
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* config.in, configure: Regenerate.
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2021-01-09 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-01-08 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2021-01-04 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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2020-02-06 Carlo Bramini <carlo_bramini@users.sourceforge.net>
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PR sim/25318
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* simulator.c (blr): Read destination register before calling
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aarch64_save_LR.
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2019-03-28 Andrew Burgess <andrew.burgess@embecosm.com>
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* cpustate.c: Add 'libiberty.h' include.
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* interp.c: Add 'sim-assert.h' include.
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2017-09-06 John Baldwin <jhb@FreeBSD.org>
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* configure: Regenerate.
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2017-04-22 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (vec_load): Add M argument. Rewrite to iterate over
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registers based on structure size.
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(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
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(LD1_1): Replace with call to vec_load.
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(vec_store): Add new M argument. Rewrite to iterate over registers
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based on structure size.
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(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
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(ST1_1): Replace with call to vec_store.
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2017-04-08 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_FCVTL): New.
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(do_vec_op1): Call do_vec_FCVTL.
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* simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
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do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
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(do_scalar_vec): Add calls to new functions.
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2017-03-25 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
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flag check.
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2017-03-03 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (mul64hi): Shift carry left by 32.
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(smulh): Change signum to negate. If negate, invert result, and add
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carry bit if low part of multiply result is zero.
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2017-02-25 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_SMOV_into_scalar): New.
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(do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
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Rewritten.
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(do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
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(do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add
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do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and
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do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call.
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* simulator.c (popcount): New.
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(do_vec_CNT): New.
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(do_vec_op1): Add do_vec_CNT call.
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2017-02-19 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
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with type set to input type size.
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(do_vec_xtl): Change bias from 3 to 4 for byte case.
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2017-02-14 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_MLA): Rewrite switch body.
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* simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and
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2. Move test_false if inside loop. Fix logic for computing result
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stored to vd.
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* simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New.
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(do_vec_LDn_single, do_vec_STn_single): New.
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(do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with
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loop over nregs using new var n. Add n times size to address in loop.
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Add n to vd in loop.
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(do_vec_load_store): Add comment for instruction bit 24. New var
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single to hold instruction bit 24. Add new code to use single. Move
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ldnr support inside single if statements. Fix ldnr register counts
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inside post if statement. Change HALT_NYI calls to HALT_UNALLOC.
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2017-01-23 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_compare): Add case 0x23 for CMTST.
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2017-01-17 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
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aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
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case 3, call HALT_UNALLOC unconditionally.
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(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
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i + 2. Delete if on bias, change index to i + bias * X.
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2017-01-09 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (do_vec_UZP): Rewrite.
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2017-01-04 Jim Wilson <jim.wilson@linaro.org>
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* cpustate.c: Include math.h.
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(aarch64_set_FP_float): Use signbit to check for signed zero.
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(aarch64_set_FP_double): Likewise.
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* simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break.
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(do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth
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args same size as third arg.
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(fmaxnm): Use isnan instead of fpclassify.
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(fminnm, dmaxnm, dminnm): Likewise.
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(do_vec_MLS): Reverse order of subtraction operands.
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(dexSimpleFPCondSelect): Call aarch64_get_FP_double or
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aarch64_get_FP_float to get source register contents.
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(UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN,
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DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN,
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DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New.
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(do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in
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raise_exception calls.
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2016-12-21 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (set_flags_for_float_compare): Add code to handle Inf.
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Add comment to document NaN issue.
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(set_flags_for_double_compare): Likewise.
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2016-12-13 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (NEG, POS): Move before set_flags_for_add64.
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(set_flags_for_add64): Replace with a modified copy of
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set_flags_for_sub64.
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2016-12-03 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting.
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(dexTestBranchImmediate): Shift high bit of pos by 5 not 4.
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2016-12-01 Jim Wilson <jim.wilson@linaro.org>
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* simulator.c (fsturs): Switch use of rn and st variables.
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(fsturd, fsturq): Likewise
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2016-08-15 Mike Frysinger <vapier@gentoo.org>
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* interp.c: Include bfd.h.
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(symcount, symtab, aarch64_get_sym_value): Delete.
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(remove_useless_symbols): Change count type to long.
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(aarch64_get_func): Add SIM_DESC to arg list. Add symcount
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and symtab local variables.
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(sim_create_inferior): Delete storage. Replace symbol code
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with a call to trace_load_symbols.
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* memory.c: Delete bfd.h, elf/internal.h, and elf/common.h
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includes.
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(aarch64_get_heap_start): Change aarch64_get_sym_value to
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trace_sym_value.
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* memory.h: Delete bfd.h include.
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(mem_add_blk): Delete unused prototype.
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* simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func.
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* simulator.c (aarch64_get_func): Add SIM_DESC to arg list.
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(aarch64_get_sym_value): Delete.
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2016-08-12 Nick Clifton <nickc@redhat.com>
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* simulator.c (aarch64_step): Revert pervious delta.
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(aarch64_run): Call sim_events_tick after each
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instruction is simulated, and if necessary call
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sim_events_process.
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* simulator.h: Revert previous delta.
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2016-08-11 Nick Clifton <nickc@redhat.com>
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* interp.c (sim_create_inferior): Allow for being called with a
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NULL abfd parameter. If a bfd is provided, initialise the sim
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with that start address.
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* simulator.c (HALT_NYI): Just print out the numeric value of the
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instruction when not tracing.
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(aarch64_step): Change from static to global.
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* simulator.h: Add a prototype for aarch64_step().
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2016-07-27 Alan Modra <amodra@gmail.com>
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* memory.c: Don't include libbfd.h.
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2016-07-21 Nick Clifton <nickc@redhat.com>
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* simulator.c (fsqrts): Use sqrtf rather than sqrt.
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2016-06-30 Jim Wilson <jim.wilson@linaro.org>
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* cpustate.h: Include config.h.
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(union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code
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use anonymous structs to align members.
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* simulator.c (aarch64_step): Use sim_core_read_buffer and
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endian_le2h_4 to read instruction from pc.
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2016-05-06 Nick Clifton <nickc@redhat.com>
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* simulator.c (do_FMLA_by_element): New function.
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(do_vec_op2): Call it.
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2016-04-27 Nick Clifton <nickc@redhat.com>
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* simulator.c: Add TRACE_DECODE statements to all emulation
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functions.
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2016-03-30 Nick Clifton <nickc@redhat.com>
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* cpustate.c (aarch64_set_reg_s32): New function.
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(aarch64_set_reg_u32): New function.
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(aarch64_get_FP_half): Place half precision value into the correct
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slot of the union.
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(aarch64_set_FP_half): Likewise.
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* cpustate.h: Add prototypes for aarch64_set_reg_s32 and
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aarch64_set_reg_u32.
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* memory.c (FETCH_FUNC): Cast the read value to the access type
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before converting it to the return type. Rename to FETCH_FUNC64.
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(FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit
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accesses. Use for 32-bit memory access functions.
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* simulator.c (ldrsb_wb): Use sign extension not zero extension.
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(ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise.
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(ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise.
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(ldrsh_scale_ext, ldrsw_abs): Likewise.
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(ldrh32_abs): Store 32 bit value not 64-bits.
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(ldrh32_wb, ldrh32_scale_ext): Likewise.
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(do_vec_MOV_immediate): Fix computation of val.
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(do_vec_MVNI): Likewise.
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(DO_VEC_WIDENING_MUL): New macro.
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(do_vec_mull): Use new macro.
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(do_vec_mul): Use new macro.
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(do_vec_MLA): Read values before writing.
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(do_vec_xtl): Likewise.
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(do_vec_SSHL): Select correct shift value.
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(do_vec_USHL): Likewise.
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(do_scalar_UCVTF): New function.
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(do_scalar_vec): Call new function.
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(store_pair_u64): Treat reads of SP as reads of XZR.
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2016-03-29 Nick Clifton <nickc@redhat.com>
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* cpustate.c: Remove space after asterisk in function parameters.
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* decode.h (greg): Delete unused function.
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(vreg, shift, extension, scaling, writeback, condcode): Likewise.
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* simulator.c: Use INSTR macro in more places.
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(HALT_NYI): Use sim_io_eprintf in place of fprintf.
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Remove extraneous whitespace.
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2016-03-23 Nick Clifton <nickc@redhat.com>
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* cpustate.c (aarch64_get_FP_half): New function. Read a vector
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register as a half precision floating point number.
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(aarch64_set_FP_half): New function. Similar, but for setting
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a half precision register.
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(aarch64_get_thread_id): New function. Returns the value of the
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CPU's TPIDR register.
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(aarch64_get_FPCR): New function. Returns the value of the CPU's
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floating point control register.
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(aarch64_set_FPCR): New function. Set the value of the CPU's FPCR
|
|
register.
|
|
* cpustate.h: Add prototypes for new functions.
|
|
* sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields.
|
|
* memory.c: Use unaligned core access functions for all memory
|
|
reads and writes.
|
|
* simulator.c (HALT_NYI): Generate an error message if tracing
|
|
will not tell the user why the simulator is halting.
|
|
(HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro.
|
|
(INSTR): New time-saver macro.
|
|
(fldrb_abs): New function. Loads an 8-bit value using a scaled
|
|
offset.
|
|
(fldrh_abs): New function. Likewise for 16-bit values.
|
|
(do_vec_SSHL): Allow for negative shift values.
|
|
(do_vec_USHL): Likewise.
|
|
(do_vec_SHL): Correct computation of shift amount.
|
|
(do_vec_SSHR_USHR): Correct decision of signed vs unsigned
|
|
shifts and computation of shift value.
|
|
(clz): New function. Counts leading zero bits.
|
|
(do_vec_CLZ): New function. Implements CLZ (vector).
|
|
(do_vec_MOV_element): Call do_vec_CLZ.
|
|
(dexSimpleFPCondCompare): Implement.
|
|
(do_FCVT_half_to_single): New function. Implements one of the
|
|
FCVT operations.
|
|
(do_FCVT_half_to_double): New function. Likewise.
|
|
(do_FCVT_single_to_half): New function. Likewise.
|
|
(do_FCVT_double_to_half): New function. Likewise.
|
|
(dexSimpleFPDataProc1Source): Call new FCVT functions.
|
|
(do_scalar_SHL): Handle negative shifts.
|
|
(do_scalar_shift): Handle SSHR.
|
|
(do_scalar_USHL): New function.
|
|
(do_double_add): Simplify to just performing a double precision
|
|
add operation. Move remaining code into...
|
|
(do_scalar_vec): ... New function.
|
|
(dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs
|
|
functions.
|
|
(system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR
|
|
registers.
|
|
(system_set): New function.
|
|
(do_MSR_immediate): New function. Stub for now.
|
|
(do_MSR_reg): New function. Likewise. Partially implements MSR
|
|
instruction.
|
|
(do_SYS): New function. Stub for now,
|
|
(dexSystem): Call new functions.
|
|
|
|
2016-03-18 Nick Clifton <nickc@redhat.com>
|
|
|
|
* cpustate.c: Remove spurious spaces from TRACE strings.
|
|
Print hex equivalents of floats and doubles.
|
|
Check element number against array size when accessing vector
|
|
registers.
|
|
(GET_VEC_ELEMENT): Fix off by one error checking for an invalid
|
|
element index.
|
|
(SET_VEC_ELEMENT): Likewise.
|
|
(GET_VEC_ELEMENT): And fix thinko using macro arguments.
|
|
|
|
* memory.c: Trace memory reads when --trace-memory is enabled.
|
|
Remove float and double load and store functions.
|
|
* memory.h (aarch64_get_mem_float): Delete prototype.
|
|
(aarch64_get_mem_double): Likewise.
|
|
(aarch64_set_mem_float): Likewise.
|
|
(aarch64_set_mem_double): Likewise.
|
|
* simulator (IS_SET): Always return either 0 or 1.
|
|
(IS_CLEAR): Likewise.
|
|
(fldrs_pcrel): Load and store floats using 32-bit memory accesses
|
|
and doubles using 64-bit memory accesses.
|
|
(fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise.
|
|
(fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise.
|
|
(fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise.
|
|
(fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise.
|
|
(store_pair_double, load_pair_float, load_pair_double): Likewise.
|
|
(do_vec_MUL_by_element): New function.
|
|
(do_vec_op2): Call do_vec_MUL_by_element.
|
|
(do_scalar_NEG): New function.
|
|
(do_double_add): Call do_scalar_NEG.
|
|
|
|
2016-03-03 Nick Clifton <nickc@redhat.com>
|
|
|
|
* simulator.c (set_flags_for_sub32): Correct type of signbit.
|
|
(CondCompare): Swap interpretation of bit 30.
|
|
(DO_ADDP): Delete macro.
|
|
(do_vec_ADDP): Copy source registers before starting to update
|
|
destination register.
|
|
(do_vec_FADDP): Likewise.
|
|
(do_vec_load_store): Fix computation of sizeof_operation.
|
|
(rbit64): Fix type of constant.
|
|
(aarch64_step): When displaying insn value, display all 32 bits.
|
|
|
|
2016-01-10 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* config.in, configure: Regenerate.
|
|
|
|
2016-01-10 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure: Regenerate.
|
|
|
|
2016-01-10 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call.
|
|
* configure: Regenerate.
|
|
|
|
2016-01-10 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure: Regenerate.
|
|
|
|
2016-01-10 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure: Regenerate.
|
|
|
|
2016-01-10 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure.ac (SIM_AC_OPTION_INLINE): Delete call.
|
|
* configure: Regenerate.
|
|
|
|
2016-01-10 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure: Regenerate.
|
|
|
|
2016-01-10 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure: Regenerate.
|
|
|
|
2016-01-09 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* config.in, configure: Regenerate.
|
|
|
|
2016-01-06 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* interp.c (sim_create_inferior): Mark argv and env const.
|
|
(sim_open): Mark argv const.
|
|
|
|
2016-01-05 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* interp.c: Delete dis-asm.h include.
|
|
(info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete.
|
|
(sim_create_inferior): Delete disassemble init logic.
|
|
(OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete.
|
|
(sim_open): Delete sim_add_option_table call.
|
|
* memory.c (mem_error): Delete disas check.
|
|
* simulator.c: Delete dis-asm.h include.
|
|
(disas): Delete.
|
|
(HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM.
|
|
(HALT_NYI): Likewise.
|
|
(handle_halt): Delete disas call.
|
|
(aarch64_step): Replace disas logic with TRACE_DISASM.
|
|
* simulator.h: Delete dis-asm.h include.
|
|
(aarch64_print_insn): Delete.
|
|
|
|
2016-01-04 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* simulator.c (MAX, MIN): Delete.
|
|
(do_vec_maxv): Change MAX to max and MIN to min.
|
|
(do_vec_fminmaxV): Likewise.
|
|
|
|
2016-01-04 Tristan Gingold <gingold@adacore.com>
|
|
|
|
* simulator.c: Remove syscall.h include.
|
|
|
|
2016-01-04 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure: Regenerate.
|
|
|
|
2016-01-03 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
|
|
* configure: Regenerate.
|
|
|
|
2016-01-02 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* configure: Regenerate.
|
|
|
|
2015-12-27 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* interp.c (sim_dis_read): Change private_data to application_data.
|
|
(sim_create_inferior): Likewise.
|
|
|
|
2015-12-27 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* Makefile.in (SIM_OBJS): Delete sim-hload.o.
|
|
|
|
2015-12-26 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* config.in, configure: Regenerate.
|
|
|
|
2015-12-26 Mike Frysinger <vapier@gentoo.org>
|
|
|
|
* interp.c (sim_create_inferior): Update comment and argv check.
|
|
|
|
2015-12-14 Nick Clifton <nickc@redhat.com>
|
|
|
|
* simulator.c (system_get): New function. Provides read
|
|
access to the dczid system register.
|
|
(do_mrs): New function - implements the MRS instruction.
|
|
(dexSystem): Call do_mrs for the MRS instruction. Halt on
|
|
unimplemented system instructions.
|
|
|
|
2015-11-24 Nick Clifton <nickc@redhat.com>
|
|
|
|
* configure.ac: New configure template.
|
|
* aclocal.m4: Generate.
|
|
* config.in: Generate.
|
|
* configure: Generate.
|
|
* cpustate.c: New file - functions for accessing AArch64 registers.
|
|
* cpustate.h: New header.
|
|
* decode.h: New header.
|
|
* interp.c: New file - interface between GDB and simulator.
|
|
* Makefile.in: New makefile template.
|
|
* memory.c: New file - functions for simulating aarch64 memory
|
|
accesses.
|
|
* memory.h: New header.
|
|
* sim-main.h: New header.
|
|
* simulator.c: New file - aarch64 simulator functions.
|
|
* simulator.h: New header.
|