375 lines
12 KiB
C
375 lines
12 KiB
C
/* Target-dependent code for the CSKY architecture, for GDB.
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Copyright (C) 2010-2022 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef CSKY_TDEP_H
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#define CSKY_TDEP_H
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#include "gdbarch.h"
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/* How to interpret the contents of the link register. */
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enum lr_type_t
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{
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LR_TYPE_R15,
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LR_TYPE_EPC,
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LR_TYPE_FPC
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};
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/* Target-dependent structure in gdbarch. */
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struct csky_gdbarch_tdep : gdbarch_tdep
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{
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/* Save FPU, VDSP ABI. */
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unsigned int fpu_abi;
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unsigned int fpu_hardfp;
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unsigned int vdsp_version;
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/* Save fv_pseudo_registers_count. */
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unsigned int has_vr0;
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unsigned int fv_pseudo_registers_count;
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};
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/* Instruction sizes. */
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enum csky_insn_size_t
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{
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CSKY_INSN_SIZE16 = 2,
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CSKY_INSN_SIZE32 = 4
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};
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/* CSKY register numbers. */
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enum csky_regnum
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{
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CSKY_R0_REGNUM = 0, /* General registers. */
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CSKY_R15_REGNUM = 15,
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CSKY_HI_REGNUM = 36,
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CSKY_LO_REGNUM = 37,
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CSKY_PC_REGNUM = 72,
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CSKY_AR0_REGNUM = 73,
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CSKY_CR0_REGNUM = 89,
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CSKY_VBR_REGNUM = CSKY_CR0_REGNUM + 1,
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CSKY_EPSR_REGNUM = CSKY_CR0_REGNUM + 2,
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CSKY_FPSR_REGNUM = CSKY_CR0_REGNUM + 3,
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CSKY_EPC_REGNUM = CSKY_CR0_REGNUM + 4,
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CSKY_FPC_REGNUM = CSKY_CR0_REGNUM + 5,
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/* Float register 0. */
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CSKY_FR0_REGNUM = 40,
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CSKY_FR16_REGNUM = 1172,
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CSKY_FCR_REGNUM = 121,
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CSKY_MMU_REGNUM = 128,
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CSKY_PROFCR_REGNUM = 140,
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CSKY_PROFGR_REGNUM = 144,
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CSKY_FP_REGNUM = 8,
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/* Vector register 0. */
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CSKY_VR0_REGNUM = 56,
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/* m32r calling convention. */
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CSKY_SP_REGNUM = CSKY_R0_REGNUM + 14,
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CSKY_RET_REGNUM = CSKY_R0_REGNUM,
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/* Argument registers. */
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CSKY_ABI_A0_REGNUM = 0,
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CSKY_ABI_LAST_ARG_REGNUM = 3,
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/* Link register, r15. */
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CSKY_LR_REGNUM = CSKY_R15_REGNUM,
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/* Processor status register, cr0. */
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CSKY_PSR_REGNUM = CSKY_CR0_REGNUM,
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CSKY_MAX_REGISTER_SIZE = 16,
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CSKY_MAX_REGS = 253
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};
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/* ICE registers. */
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#define CSKY_CRBANK_NUM_REGS 32
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/* Tdesc registers essential check. */
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#define CSKY_TDESC_REGS_PC_NUMBERED (1 << 0)
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#define CSKY_TDESC_REGS_SP_NUMBERED (1 << 1)
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#define CSKY_TDESC_REGS_LR_NUMBERED (1 << 2)
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#define CSKY_TDESC_REGS_ESSENTIAL_VALUE (7)
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/* For fr0~fr15, fr16~fr31, vr0~vr15 check. */
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#define CSKY_FULL16_ONEHOT_VALUE 0xffff
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/* Number of processor registers w/o ICE registers. */
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#define CSKY_NUM_REGS (CSKY_MAX_REGS - CSKY_CRBANK_NUM_REGS)
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/* size. */
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#define CSKY_16_ST_SIZE(insn) (1 << ((insn & 0x1800) >> 11))
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/* rx. */
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#define CSKY_16_ST_ADDR_REGNUM(insn) ((insn & 0x700) >> 8)
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/* disp. */
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#define CSKY_16_ST_OFFSET(insn) ((insn & 0x1f) << ((insn & 0x1800) >> 11))
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/* ry. */
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#define CSKY_16_ST_VAL_REGNUM(insn) ((insn & 0xe0) >> 5)
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/* st16.w rz, (sp, disp). */
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#define CSKY_16_IS_STWx0(insn) ((insn & 0xf800) == 0xb800)
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#define CSKY_16_STWx0_VAL_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn)
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/* disp. */
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#define CSKY_16_STWx0_OFFSET(insn) \
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((((insn & 0x700) >> 3) + (insn & 0x1f)) << 2)
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/* Check ld16 but not ld16 sp. */
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#define CSKY_16_IS_LD(insn) \
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(((insn & 0xe000) == 0x8000) && (insn & 0x1800) != 0x1800)
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/* size. */
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#define CSKY_16_LD_SIZE(insn) CSKY_16_ST_SIZE (insn)
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/* rx. */
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#define CSKY_16_LD_ADDR_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn)
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/* disp. */
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#define CSKY_16_LD_OFFSET(insn) CSKY_16_ST_OFFSET (insn)
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/* ld16.w rz,(sp,disp). */
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#define CSKY_16_IS_LDWx0(insn) ((insn & 0xf800) == 0x9800)
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/*disp. */
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#define CSKY_16_LDWx0_OFFSET(insn) CSKY_16_STWx0_OFFSET (insn)
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/* st32.b/h/w/d. */
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#define CSKY_32_IS_ST(insn) ((insn & 0xfc00c000) == 0xdc000000)
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/* size: b/h/w/d. */
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#define CSKY_32_ST_SIZE(insn) (1 << ((insn & 0x3000) >> 12))
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/* rx. */
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#define CSKY_32_ST_ADDR_REGNUM(insn) ((insn & 0x001f0000) >> 16)
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/* disp. */
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#define CSKY_32_ST_OFFSET(insn) ((insn & 0xfff) << ((insn & 0x3000) >> 12))
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/* ry. */
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#define CSKY_32_ST_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21)
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/* stw ry, (sp, disp). */
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#define CSKY_32_IS_STWx0(insn) ((insn & 0xfc1ff000) == 0xdc0e2000)
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/* stm32 ry-rz, (rx). */
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#define CSKY_32_IS_STM(insn) ((insn & 0xfc00ffe0) == 0xd4001c20)
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/* rx. */
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#define CSKY_32_STM_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
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/* Count of registers. */
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#define CSKY_32_STM_SIZE(insn) (insn & 0x1f)
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/* ry. */
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#define CSKY_32_STM_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21)
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/* stm32 ry-rz, (sp). */
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#define CSKY_32_IS_STMx0(insn) ((insn & 0xfc1fffe0) == 0xd40e1c20)
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/* str32.b/h/w rz, (rx, ry << offset). */
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#define CSKY_32_IS_STR(insn) \
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(((insn & 0xfc000000) == 0xd4000000) && !(CSKY_32_IS_STM (insn)))
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/* rx. */
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#define CSKY_32_STR_X_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
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/* ry. */
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#define CSKY_32_STR_Y_REGNUM(insn) ((insn >> 21) & 0x1f)
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/* size: b/h/w. */
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#define CSKY_32_STR_SIZE(insn) (1 << ((insn & 0x0c00) >> 10))
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/* imm (for rx + ry * imm). */
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#define CSKY_32_STR_OFFSET(insn) ((insn & 0x000003e0) >> 5)
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/* stex32.w rz, (rx, disp). */
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#define CSKY_32_IS_STEX(insn) ((insn & 0xfc00f000) == 0xdc007000)
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/* rx. */
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#define CSKY_32_STEX_ADDR_REGNUM(insn) ((insn & 0x1f0000) >> 16)
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/* disp. */
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#define CSKY_32_STEX_OFFSET(insn) ((insn & 0x0fff) << 2)
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/* ld.b/h/w. */
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#define CSKY_32_IS_LD(insn) ((insn & 0xfc00c000) == 0xd8000000)
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/* size. */
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#define CSKY_32_LD_SIZE(insn) CSKY_32_ST_SIZE (insn)
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/* rx. */
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#define CSKY_32_LD_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn)
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/* disp. */
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#define CSKY_32_LD_OFFSET(insn) CSKY_32_ST_OFFSET (insn)
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#define CSKY_32_IS_LDM(insn) ((insn & 0xfc00ffe0) == 0xd0001c20)
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/* rx. */
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#define CSKY_32_LDM_ADDR_REGNUM(insn) CSKY_32_STM_ADDR_REGNUM (insn)
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/* Count of registers. */
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#define CSKY_32_LDM_SIZE(insn) CSKY_32_STM_SIZE (insn)
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/* ldr32.b/h/w rz, (rx, ry << offset). */
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#define CSKY_32_IS_LDR(insn) \
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(((insn & 0xfc00fe00) == 0xd0000000) && !(CSKY_32_IS_LDM (insn)))
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/* rx. */
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#define CSKY_32_LDR_X_REGNUM(insn) CSKY_32_STR_X_REGNUM (insn)
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/* ry. */
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#define CSKY_32_LDR_Y_REGNUM(insn) CSKY_32_STR_Y_REGNUM (insn)
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/* size: b/h/w. */
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#define CSKY_32_LDR_SIZE(insn) CSKY_32_STR_SIZE (insn)
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/* imm (for rx + ry*imm). */
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#define CSKY_32_LDR_OFFSET(insn) CSKY_32_STR_OFFSET (insn)
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#define CSKY_32_IS_LDEX(insn) ((insn & 0xfc00f000) == 0xd8007000)
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/* rx. */
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#define CSKY_32_LDEX_ADDR_REGNUM(insn) CSKY_32_STEX_ADDR_REGNUM (insn)
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/* disp. */
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#define CSKY_32_LDEX_OFFSET(insn) CSKY_32_STEX_OFFSET (insn)
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/* subi.sp sp, disp. */
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#define CSKY_16_IS_SUBI0(insn) ((insn & 0xfce0) == 0x1420)
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/* disp. */
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#define CSKY_16_SUBI_IMM(insn) ((((insn & 0x300) >> 3) + (insn & 0x1f)) << 2)
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/* subi32 sp,sp,oimm12. */
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#define CSKY_32_IS_SUBI0(insn) ((insn & 0xfffff000) == 0xe5ce1000)
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/* oimm12. */
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#define CSKY_32_SUBI_IMM(insn) ((insn & 0xfff) + 1)
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/* push16. */
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#define CSKY_16_IS_PUSH(insn) ((insn & 0xffe0) == 0x14c0)
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#define CSKY_16_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10)
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#define CSKY_16_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11. */
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/* pop16. */
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#define CSKY_16_IS_POP(insn) ((insn & 0xffe0) == 0x1480)
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#define CSKY_16_IS_POP_R15(insn) CSKY_16_IS_PUSH_R15 (insn)
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#define CSKY_16_POP_LIST1(insn) CSKY_16_PUSH_LIST1 (insn) /* r4 - r11. */
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/* push32. */
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#define CSKY_32_IS_PUSH(insn) ((insn & 0xfffffe00) == 0xebe00000)
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#define CSKY_32_IS_PUSH_R29(insn) ((insn & 0x100) == 0x100)
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#define CSKY_32_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10)
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#define CSKY_32_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11. */
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#define CSKY_32_PUSH_LIST2(insn) ((insn & 0xe0) >> 5) /* r16 - r17. */
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/* pop32. */
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#define CSKY_32_IS_POP(insn) ((insn & 0xfffffe00) == 0xebc00000)
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#define CSKY_32_IS_POP_R29(insn) CSKY_32_IS_PUSH_R29 (insn)
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#define CSKY_32_IS_POP_R15(insn) CSKY_32_IS_PUSH_R15 (insn)
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#define CSKY_32_POP_LIST1(insn) CSKY_32_PUSH_LIST1 (insn) /* r4 - r11. */
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#define CSKY_32_POP_LIST2(insn) CSKY_32_PUSH_LIST2 (insn) /* r16 - r17. */
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/* Adjust sp by r4(l0). */
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/* lrw r4, literal. */
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#define CSKY_16_IS_LRW4(x) (((x) &0xfce0) == 0x1080)
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/* movi r4, imm8. */
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#define CSKY_16_IS_MOVI4(x) (((x) &0xff00) == 0x3400)
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/* addi r4, oimm8. */
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#define CSKY_16_IS_ADDI4(x) (((x) &0xff00) == 0x2400)
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/* subi r4, oimm8. */
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#define CSKY_16_IS_SUBI4(x) (((x) &0xff00) == 0x2c00)
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/* nor16 r4, r4. */
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#define CSKY_16_IS_NOR4(x) ((x) == 0x6d12)
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/* lsli r4, r4, imm5. */
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#define CSKY_16_IS_LSLI4(x) (((x) &0xffe0) == 0x4480)
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/* bseti r4, imm5. */
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#define CSKY_16_IS_BSETI4(x) (((x) &0xffe0) == 0x3ca0)
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/* bclri r4, imm5. */
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#define CSKY_16_IS_BCLRI4(x) (((x) &0xffe0) == 0x3c80)
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/* subu sp, r4. */
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#define CSKY_16_IS_SUBU4(x) ((x) == 0x6392)
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#define CSKY_16_IS_R4_ADJUSTER(x) \
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(CSKY_16_IS_ADDI4 (x) || CSKY_16_IS_SUBI4 (x) || CSKY_16_IS_BSETI4 (x) \
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|| CSKY_16_IS_BCLRI4 (x) || CSKY_16_IS_NOR4 (x) || CSKY_16_IS_LSLI4 (x))
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/* lrw r4, literal. */
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#define CSKY_32_IS_LRW4(x) (((x) &0xffff0000) == 0xea840000)
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/* movi r4, imm16. */
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#define CSKY_32_IS_MOVI4(x) (((x) &0xffff0000) == 0xea040000)
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/* movih r4, imm16. */
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#define CSKY_32_IS_MOVIH4(x) (((x) &0xffff0000) == 0xea240000)
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/* bmaski r4, oimm5. */
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#define CSKY_32_IS_BMASKI4(x) (((x) &0xfc1fffff) == 0xc4005024)
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/* addi r4, r4, oimm12. */
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#define CSKY_32_IS_ADDI4(x) (((x) &0xfffff000) == 0xe4840000)
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/* subi r4, r4, oimm12. */
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#define CSKY_32_IS_SUBI4(x) (((x) &0xfffff000) == 0xe4810000)
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/* nor32 r4, r4, r4. */
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#define CSKY_32_IS_NOR4(x) ((x) == 0xc4842484)
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/* rotli r4, r4, imm5. */
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#define CSKY_32_IS_ROTLI4(x) (((x) &0xfc1fffff) == 0xc4044904)
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/* lsli r4, r4, imm5. */
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#define CSKY_32_IS_LISI4(x) (((x) &0xfc1fffff) == 0xc4044824)
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/* bseti32 r4, r4, imm5. */
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#define CSKY_32_IS_BSETI4(x) (((x) &0xfc1fffff) == 0xc4042844)
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/* bclri32 r4, r4, imm5. */
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#define CSKY_32_IS_BCLRI4(x) (((x) &0xfc1fffff) == 0xc4042824)
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/* ixh r4, r4, r4. */
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#define CSKY_32_IS_IXH4(x) ((x) == 0xc4840824)
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/* ixw r4, r4, r4. */
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#define CSKY_32_IS_IXW4(x) ((x) == 0xc4840844)
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/* subu32 sp, sp, r4. */
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#define CSKY_32_IS_SUBU4(x) ((x) == 0xc48e008e)
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#define CSKY_32_IS_R4_ADJUSTER(x) \
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(CSKY_32_IS_ADDI4 (x) || CSKY_32_IS_SUBI4 (x) || CSKY_32_IS_ROTLI4 (x) \
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|| CSKY_32_IS_IXH4 (x) || CSKY_32_IS_IXW4 (x) || CSKY_32_IS_NOR4 (x) \
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|| CSKY_32_IS_BSETI4 (x) || CSKY_32_IS_BCLRI4 (x) || CSKY_32_IS_LISI4 (x))
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#define CSKY_IS_R4_ADJUSTER(x) \
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(CSKY_32_IS_R4_ADJUSTER (x) || CSKY_16_IS_R4_ADJUSTER (x))
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#define CSKY_IS_SUBU4(x) (CSKY_32_IS_SUBU4 (x) || CSKY_16_IS_SUBU4 (x))
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/* mfcr rz, epsr. */
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#define CSKY_32_IS_MFCR_EPSR(insn) ((insn & 0xffffffe0) == 0xc0026020)
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/* mfcr rz, fpsr. */
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#define CSKY_32_IS_MFCR_FPSR(insn) ((insn & 0xffffffe0) == 0xc0036020)
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/* mfcr rz, epc. */
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#define CSKY_32_IS_MFCR_EPC(insn) ((insn & 0xffffffe0) == 0xc0046020)
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/* mfcr rz, fpc. */
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#define CSKY_32_IS_MFCR_FPC(insn) ((insn & 0xffffffe0) == 0xc0056020)
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#define CSKY_32_IS_RTE(insn) (insn == 0xc0004020)
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#define CSKY_32_IS_RFI(insn) (insn == 0xc0004420)
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#define CSKY_32_IS_JMP(insn) ((insn & 0xffe0ffff) == 0xe8c00000)
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#define CSKY_16_IS_JMP(insn) ((insn & 0xffc3) == 0x7800)
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#define CSKY_32_IS_JMPI(insn) ((insn & 0xffff0000) == 0xeac00000)
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#define CSKY_32_IS_JMPIX(insn) ((insn & 0xffe0fffc) == 0xe9e00000)
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#define CSKY_16_IS_JMPIX(insn) ((insn & 0xf8fc) == 0x38e0)
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#define CSKY_16_IS_BR(insn) ((insn & 0xfc00) == 0x0400)
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#define CSKY_32_IS_BR(insn) ((insn & 0xffff0000) == 0xe8000000)
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#define CSKY_16_IS_MOV_FP_SP(insn) (insn == 0x6e3b) /* mov r8, r14. */
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#define CSKY_32_IS_MOV_FP_SP(insn) (insn == 0xc40e4828) /* mov r8, r14. */
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#define CSKY_16_IS_MOV_SP_FP(insn) (insn == 0x6fa3) /* mov r14, r8. */
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#define CSKY_32_INSN_MASK 0xc000
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#define CSKY_BKPT_INSN 0x0
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#define CSKY_NUM_GREGS 32
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/* 32 general regs + 4. */
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#define CSKY_NUM_GREGS_SAVED_GREGS (CSKY_NUM_GREGS + 4)
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/* CSKY software bkpt write-mode. */
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#define CSKY_WR_BKPT_MODE 4
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/* Define insns for parse rt_sigframe. */
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/* There are three words(sig, pinfo, puc) before siginfo. */
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#define CSKY_SIGINFO_OFFSET 0xc
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/* Size of struct siginfo. */
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#define CSKY_SIGINFO_SIZE 0x80
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/* There are five words(uc_flags, uc_link, and three for uc_stack)
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in struct ucontext before sigcontext. */
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#define CSKY_UCONTEXT_SIGCONTEXT 0x14
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/* There is a word(sc_mask) before sc_usp. */
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#define CSKY_SIGCONTEXT_SC_USP 0x4
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/* There is a word(sc_usp) before sc_a0. */
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#define CSKY_SIGCONTEXT_SC_A0 0x4
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#define CSKY_MOVI_R7_173 0x00adea07
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#define CSKY_TRAP_0 0x2020c000
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#endif
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