426 lines
13 KiB
Scheme
426 lines
13 KiB
Scheme
; OpenRISC 1000 32-bit CPU hardware description. -*- Scheme -*-
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; Copyright 2000-2019 Free Software Foundation, Inc.
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; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
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; Modified by Julius Baxter, juliusbaxter@gmail.com
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; Modified by Andrey Bacherov, avbacherov@opencores.org
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, see <http://www.gnu.org/licenses/>
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; Hardware pieces.
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; These entries list the elements of the raw hardware.
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; They're also used to provide tables and other elements of the assembly
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; language.
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(define-hardware
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(name h-pc)
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(comment "program counter")
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(attrs PC (MACH ORBIS-MACHS))
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(type pc UWI)
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(get () (raw-reg h-pc))
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(set (newval) (sequence ()
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(set (reg h-sys-ppc) (raw-reg h-pc))
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(set (raw-reg h-pc) newval)
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))
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)
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(define-pmacro REG-INDICES
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((r0 0)
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(r1 1)
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(r2 2)
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(r3 3)
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(r4 4)
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(r5 5)
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(r6 6)
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(r7 7)
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(r8 8)
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(r9 9)
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(r10 10)
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(r11 11)
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(r12 12)
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(r13 13)
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(r14 14)
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(r15 15)
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(r16 16)
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(r17 17)
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(r18 18)
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(r19 19)
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(r20 20)
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(r21 21)
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(r22 22)
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(r23 23)
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(r24 24)
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(r25 25)
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(r26 26)
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(r27 27)
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(r28 28)
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(r29 29)
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(r30 30)
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(r31 31)
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(lr 9)
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(sp 1)
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(fp 2))
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)
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;
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; Hardware: [S]pecial [P]urpose [R]egisters
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;
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(define-hardware
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(name h-spr) (comment "special purpose registers")
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(attrs VIRTUAL (MACH ORBIS-MACHS))
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(type register UWI (#x20000))
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(get (index) (c-call UWI "@cpu@_h_spr_get_raw" index))
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(set (index newval) (c-call VOID "@cpu@_h_spr_set_raw" index newval))
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)
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(define-pmacro spr-shift 11)
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(define-pmacro (spr-address spr-group spr-index)
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(or (sll UWI (enum UWI (.sym "SPR-GROUP-" spr-group)) spr-shift)
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(enum UWI (.sym "SPR-INDEX-" spr-group "-" spr-index))))
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;
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; Hardware: [G]enepral [P]urpose [R]egisters
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;
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(define-hardware
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(name h-gpr) (comment "general registers")
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(attrs (MACH ORBIS-MACHS))
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(type register UWI (32))
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(indices keyword "" REG-INDICES)
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(get (index) (reg UWI h-spr (add index (spr-address SYS GPR0))))
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(set (index newval) (set UWI (reg UWI h-spr (add index (spr-address SYS GPR0))) newval))
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)
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;
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; Hardware: virtual registerts for FPU (single precision)
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; mapped to GPRs
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;
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(define-hardware
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(name h-fsr)
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(comment "floating point registers (single, virtual)")
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(attrs VIRTUAL (MACH ORFPX32-MACHS))
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(type register SF (32))
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(indices keyword "" REG-INDICES)
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(get (index) (subword SF (trunc SI (reg h-gpr index)) 0))
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(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
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)
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;
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; Register pairs are offset by 2 for registers r16 and above. This is to
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; be able to allow registers to be call saved in GCC across function calls.
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;
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(define-pmacro (reg-pair-reg-lo index)
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(and index (const #x1f))
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)
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(define-pmacro (reg-pair-reg-hi index)
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(add (and index (const #x1f))
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(if (eq (sra index (const 5))
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(const 1))
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(const 2)
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(const 1)
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)
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)
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)
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;
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; Hardware: vrtual registers for double precision floating point
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; operands on 32-bit machines
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; mapped to GPRs
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;
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(define-hardware
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(name h-fd32r)
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(comment "or32 floating point registers (double, virtual)")
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(attrs VIRTUAL (MACH ORFPX64A32-MACHS))
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(type register DF (32))
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(get (index) (join DF SI
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(reg h-gpr (reg-pair-reg-lo index))
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(reg h-gpr (reg-pair-reg-hi index))))
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(set (index newval)
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(sequence ()
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(set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
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(set (reg h-gpr (reg-pair-reg-hi index))
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(subword SI newval 1))))
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)
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;
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; Hardware: vrtual 64-bit integer registers for conversions
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; float64 <-> int64 on 32-bit machines
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; mapped to GPRs
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;
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(define-hardware
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(name h-i64r)
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(comment "or32 double word registers (int64, virtual)")
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(attrs VIRTUAL (MACH ORFPX64A32-MACHS))
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(type register DI (32))
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(get (index) (join DI SI
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(reg h-gpr (reg-pair-reg-lo index))
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(reg h-gpr (reg-pair-reg-hi index))))
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(set (index newval)
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(sequence ()
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(set (reg h-gpr (reg-pair-reg-lo index)) (subword SI newval 0))
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(set (reg h-gpr (reg-pair-reg-hi index))
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(subword SI newval 1))))
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)
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(define-normal-enum
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except-number
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"Exception numbers"
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()
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EXCEPT-
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(("NONE" #x00)
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("RESET" #x01)
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("BUSERR" #x02)
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("DPF" #x03)
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("IPF" #x04)
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("TICK" #x05)
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("ALIGN" #x06)
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("ILLEGAL" #x07)
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("INT" #x08)
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("DTLBMISS" #x09)
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("ITLBMISS" #x0a)
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("RANGE" #x0b)
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("SYSCALL" #x0c)
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("FPE" #x0d)
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("TRAP" #x0e)
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)
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)
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(define-pmacro (raise-exception exnum)
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(c-call VOID "@cpu@_exception" pc exnum))
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(define-normal-enum
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spr-groups
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"special purpose register groups"
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()
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SPR-GROUP-
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(("SYS" #x0)
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("DMMU" #x1)
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("IMMU" #x2)
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("DCACHE" #x3)
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("ICACHE" #x4)
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("MAC" #x5)
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("DEBUG" #x6)
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("PERF" #x7)
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("POWER" #x8)
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("PIC" #x9)
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("TICK" #xa)
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("FPU" #xb)
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)
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)
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(define-pmacro (spr-reg-info)
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(.splice
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(SYS VR #x000 "version register")
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(SYS UPR #x001 "unit present register")
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(SYS CPUCFGR #x002 "cpu configuration register")
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(SYS DMMUCFGR #x003 "Data MMU configuration register")
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(SYS IMMUCFGR #x004 "Insn MMU configuration register")
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(SYS DCCFGR #x005 "Data cache configuration register")
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(SYS ICCFGR #x006 "Insn cache configuration register")
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(SYS DCFGR #x007 "Debug configuration register")
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(SYS PCCFGR #x008 "Performance counters configuration register")
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(SYS NPC #x010 "Next program counter")
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(SYS SR #x011 "Supervision Register")
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(SYS PPC #x012 "Previous program counter")
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(SYS FPCSR #x014 "Floating point control status register")
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(.unsplice
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(.map (.pmacro (n) (.splice SYS (.sym "EPCR" n) (.add n #x20) (.str "Exception PC register " n)))
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(.iota #x10)))
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(.unsplice
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(.map (.pmacro (n) (.splice SYS (.sym "EEAR" n) (.add n #x30) (.str "Exception effective address register " n)))
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(.iota #x10)))
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(.unsplice
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(.map (.pmacro (n) (.splice SYS (.sym "ESR" n) (.add n #x40) (.str "Exception supervision register " n)))
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(.iota #x10)))
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(.unsplice
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(.map (.pmacro (n) (.splice SYS (.sym "GPR" n) (.add n #x400) (.str "General purpose register " n)))
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(.iota #x200)))
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(MAC MACLO #x001 "Multiply and accumulate result (low)")
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(MAC MACHI #x002 "Multiply and accumulate result (high)")
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(TICK TTMR #x000 "Tick timer mode register")
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)
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)
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(define-normal-enum
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spr-reg-indices
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"special purpose register indices"
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()
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SPR-INDEX-
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(.map (.pmacro (args)
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(.apply (.pmacro (group index n comment)
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((.sym group "-" index) n))
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args)
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)
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(spr-reg-info)
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)
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)
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(define-pmacro (define-h-spr-reg spr-group spr-index n spr-comment)
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(define-hardware
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(name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index)))
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(comment spr-comment)
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(attrs VIRTUAL (MACH ORBIS-MACHS))
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(type register UWI)
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(get () (reg UWI h-spr (spr-address spr-group spr-index)))
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(set (newval) (set (reg UWI h-spr (spr-address spr-group spr-index)) newval))
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)
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)
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(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-reg args)) (spr-reg-info))))
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(define-pmacro (spr-field-info)
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((SYS VR REV 5 0 "revision field")
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(SYS VR CFG 23 16 "configuration template field")
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(SYS VR VER 31 24 "version field")
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(SYS UPR UP 0 0 "UPR present bit")
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(SYS UPR DCP 1 1 "data cache present bit")
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(SYS UPR ICP 2 2 "insn cache present bit")
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(SYS UPR DMP 3 3 "data MMU present bit")
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(SYS UPR MP 4 4 "MAC unit present bit")
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(SYS UPR IMP 5 5 "insn MMU present bit")
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(SYS UPR DUP 6 6 "debug unit present bit")
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(SYS UPR PCUP 7 7 "performance counters unit present bit")
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(SYS UPR PICP 8 8 "programmable interrupt controller present bit")
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(SYS UPR PMP 9 9 "power management present bit")
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(SYS UPR TTP 10 10 "tick timer present bit")
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(SYS UPR CUP 31 24 "custom units present field")
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(SYS CPUCFGR NSGR 3 0 "number of shadow GPR files field")
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(SYS CPUCFGR CGF 4 4 "custom GPR file bit")
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(SYS CPUCFGR OB32S 5 5 "ORBIS32 supported bit")
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(SYS CPUCFGR OB64S 6 6 "ORBIS64 supported bit")
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(SYS CPUCFGR OF32S 7 7 "ORFPX32 supported bit")
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(SYS CPUCFGR OF64S 8 8 "ORFPX64 supported bit")
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(SYS CPUCFGR OV64S 9 9 "ORVDX64 supported bit")
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(SYS CPUCFGR ND 10 10 "no transfer delay bit")
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(SYS SR SM 0 0 "supervisor mode bit")
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(SYS SR TEE 1 1 "tick timer exception enabled bit")
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(SYS SR IEE 2 2 "interrupt exception enabled bit")
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(SYS SR DCE 3 3 "data cache enabled bit")
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(SYS SR ICE 4 4 "insn cache enabled bit")
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(SYS SR DME 5 5 "data MMU enabled bit")
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(SYS SR IME 6 6 "insn MMU enabled bit")
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(SYS SR LEE 7 7 "little endian enabled bit")
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(SYS SR CE 8 8 "CID enable bit")
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(SYS SR F 9 9 "flag bit")
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(SYS SR CY 10 10 "carry bit")
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(SYS SR OV 11 11 "overflow bit")
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(SYS SR OVE 12 12 "overflow exception enabled bit")
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(SYS SR DSX 13 13 "delay slot exception bit")
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(SYS SR EPH 14 14 "exception prefix high bit")
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(SYS SR FO 15 15 "fixed one bit")
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(SYS SR SUMRA 16 16 "SPRs user mode read access bit")
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(SYS SR CID 31 28 "context ID field")
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(SYS FPCSR FPEE 0 0 "floating point exceptions enabled bit")
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(SYS FPCSR RM 2 1 "floating point rounding mode field")
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(SYS FPCSR OVF 3 3 "floating point overflow flag bit")
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(SYS FPCSR UNF 4 4 "floating point underflow bit")
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(SYS FPCSR SNF 5 5 "floating point SNAN flag bit")
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(SYS FPCSR QNF 6 6 "floating point QNAN flag bit")
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(SYS FPCSR ZF 7 7 "floating point zero flag bit")
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(SYS FPCSR IXF 8 8 "floating point inexact flag bit")
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(SYS FPCSR IVF 9 9 "floating point invalid flag bit")
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(SYS FPCSR INF 10 10 "floating point infinity flag bit")
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(SYS FPCSR DZF 11 11 "floating point divide by zero flag bit")
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)
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)
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(define-normal-enum
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spr-field-msbs
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"SPR field msb positions"
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()
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SPR-FIELD-MSB-
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(.map (.pmacro (args)
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(.apply (.pmacro (group index field msb lsb comment)
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((.sym group "-" index "-" field) msb)
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)
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args
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)
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)
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(spr-field-info)
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)
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)
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(define-normal-enum
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spr-field-lsbs
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"SPR field lsb positions"
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()
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SPR-FIELD-SIZE-
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(.map (.pmacro (args)
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(.apply (.pmacro (group index field msb lsb comment)
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((.sym group "-" index "-" field) lsb)
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)
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args
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)
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)
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(spr-field-info)
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)
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)
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(define-normal-enum
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spr-field-masks
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"SPR field masks"
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()
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SPR-FIELD-MASK-
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(.map (.pmacro (args)
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(.apply (.pmacro (group index field msb lsb comment)
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(.splice (.str group "-" index "-" field) (.sll (.inv (.sll (.inv 0) (.add (.sub msb lsb) 1))) lsb))
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)
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args
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)
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)
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(spr-field-info)
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)
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)
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(define-pmacro (define-h-spr-field spr-group spr-index spr-field spr-field-msb spr-field-lsb spr-field-comment)
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(.let ((spr-field-name (.sym "h-" (.downcase spr-group) "-" (.downcase spr-index) "-" (.downcase spr-field)))
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)
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(begin
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(define-hardware
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(name spr-field-name)
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(comment spr-field-comment)
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(attrs VIRTUAL (MACH ORBIS-MACHS))
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(type register UWI)
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(get () (c-call UWI "@cpu@_h_spr_field_get_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb))
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(set (value) (c-call VOID "@cpu@_h_spr_field_set_raw" (spr-address spr-group spr-index) spr-field-msb spr-field-lsb value))
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)
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)
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)
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)
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(.splice begin (.unsplice (.map (.pmacro (args) (.apply define-h-spr-field args)) (spr-field-info))))
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(define-attr
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(type boolean)
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(for insn)
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(name DELAYED-CTI)
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(comment "delayed control transfer instruction")
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(values #f #t)
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(default #f)
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)
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(define-attr
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(for insn)
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(type boolean)
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(name NOT-IN-DELAY-SLOT)
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(comment "instruction cannot be in delay slot")
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(values #f #t)
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(default #f)
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)
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(define-attr
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(for insn)
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(type boolean)
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(name FORCED-CTI)
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(comment "instruction may forcefully transfer control (e.g., rfe)")
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)
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