340 lines
13 KiB
Scheme
340 lines
13 KiB
Scheme
; Toshiba MeP FMAX Coprocessor description. -*- Scheme -*-
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; Copyright 2011 Free Software Foundation, Inc.
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;
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; Contributed by Red Hat Inc;
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;
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; This file is part of the GNU Binutils.
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, write to the Free Software
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; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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; MA 02110-1301, USA.
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;------------------------------------------------------------------------------
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; MeP-Integrator will redefine the isa pmacros below to allow the bit widths
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; specified below for each ME_MODULE using this coprocessor.
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; This coprocessor requires only the 32 bit insns in the core.
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;------------------------------------------------------------------------------
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; begin-isas
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(define-pmacro fmax-core-isa () (ISA ext_core2))
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(define-pmacro all-fmax-isas () (ISA ext_core2))
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; end-isas
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;******************************************************************************
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; ifields
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;------------------------------------------------------------------------------
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; opcodes
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(dnf f-fmax-0-4 "opcode" (all-fmax-isas) 0 4)
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(dnf f-fmax-4-4 "opcode" (all-fmax-isas) 4 4)
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(dnf f-fmax-8-4 "opcode" (all-fmax-isas) 8 4)
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(dnf f-fmax-12-4 "opcode" (all-fmax-isas) 12 4)
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(dnf f-fmax-16-4 "opcode" (all-fmax-isas) 16 4)
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(dnf f-fmax-20-4 "opcode" (all-fmax-isas) 20 4)
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(dnf f-fmax-24-4 "opcode" (all-fmax-isas) 24 4)
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(dnf f-fmax-28-1 "opcode" (all-fmax-isas) 28 1)
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(dnf f-fmax-29-1 "opcode" (all-fmax-isas) 29 1)
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(dnf f-fmax-30-1 "opcode" (all-fmax-isas) 30 1)
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(dnf f-fmax-31-1 "opcode" (all-fmax-isas) 31 1)
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;------------------------------------------------------------------------------
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; FR registers
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(define-multi-ifield
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(name f-fmax-frd)
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(comment "FRd register")
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(attrs all-fmax-isas)
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(mode UINT)
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(subfields f-fmax-28-1 f-fmax-4-4)
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(insert (sequence ()
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(set (ifield f-fmax-4-4) (and (ifield f-fmax-frd) #xf))
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(set (ifield f-fmax-28-1) (srl (ifield f-fmax-frd) 4))))
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(extract (set (ifield f-fmax-frd)
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(or (sll (ifield f-fmax-28-1) 4) (ifield f-fmax-4-4))))
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)
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(define-multi-ifield
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(name f-fmax-frn)
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(comment "FRn register")
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(attrs all-fmax-isas)
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(mode UINT)
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(subfields f-fmax-29-1 f-fmax-20-4)
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(insert (sequence ()
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(set (ifield f-fmax-20-4) (and (ifield f-fmax-frn) #xf))
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(set (ifield f-fmax-29-1) (srl (ifield f-fmax-frn) 4))))
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(extract (set (ifield f-fmax-frn)
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(or (sll (ifield f-fmax-29-1) 4) (ifield f-fmax-20-4))))
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)
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(define-multi-ifield
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(name f-fmax-frm)
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(comment "FRm register")
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(attrs all-fmax-isas)
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(mode UINT)
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(subfields f-fmax-30-1 f-fmax-24-4)
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(insert (sequence ()
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(set (ifield f-fmax-24-4) (and (ifield f-fmax-frm) #xf))
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(set (ifield f-fmax-30-1) (srl (ifield f-fmax-frm) 4))))
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(extract (set (ifield f-fmax-frm)
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(or (sll (ifield f-fmax-30-1) 4) (ifield f-fmax-24-4))))
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)
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;------------------------------------------------------------------------------
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; Core General registers
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(dnf f-fmax-rm "opcode" (all-fmax-isas) 8 4)
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;------------------------------------------------------------------------------
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; Condition opcodes enum
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(define-normal-insn-enum fmax-cond "condition opcode enum" (all-fmax-isas) FMAX_ f-fmax-8-4
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("f" "u" "e" "ue" "l" "ul" "le" "ule"
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"fi" "ui" "ei" "uei" "li" "uli" "lei" "ulei")
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)
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;******************************************************************************
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; Hardware
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;------------------------------------------------------------------------------
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; FR registers
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; Given a coprocessor register number N, expand to a
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; name/index pair: ($frN N)
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(define-pmacro (-fmax-fr-reg-pair n) ((.sym "fr" n) n))
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(define-pmacro (-fmax-cr-reg-pair n) ((.sym "c" n) n))
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; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
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; GDB will use the hardware table generated from this declaration. The operands use h-cr
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; from mep-core.cpu so that SID's semantic trace will be consistent between
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; the core and the coprocessor but use parse/print handlers which reference the hardware table
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; generated from this declarations
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(define-hardware
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(name h-cr-fmax)
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(comment "Floating point registers")
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(attrs all-fmax-isas VIRTUAL IS_FLOAT)
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(type register SF (32))
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(indices keyword "$"
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(.splice (.unsplice (.map -fmax-fr-reg-pair (.iota 32)))
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(.unsplice (.map -fmax-cr-reg-pair (.iota 32))))
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)
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(get (index) (c-call SF "fmax_fr_get_handler" index))
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(set (index newval) (c-call VOID "fmax_fr_set_handler" index newval))
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)
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;------------------------------------------------------------------------------
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; Control registers
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; NOTE: This exists solely for the purpose of providing the proper register names for this coprocessor.
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; GDB will use the hardware table generated from this declaration. The operands use h-ccr
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; from mep-core.cpu so that SID's semantic trace will be consistent between
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; the core and the coprocessor but use parse/print handlers which reference the hardware table
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; generated from this declarations
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(define-hardware
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(name h-ccr-fmax)
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(comment "Coprocessor Identifier and Revision Register")
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(attrs all-fmax-isas VIRTUAL)
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(type register USI (16))
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(indices keyword "$" (
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("cirr" 0) ("fcr0" 0) ("ccr0" 0)
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("cbcr" 1) ("fcr1" 1) ("ccr1" 1)
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("cerr" 15) ("fcr15" 15) ("ccr15" 15)
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)
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)
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(set (index newval) (c-call VOID "h_ccr_set" index newval))
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(get (index) (c-call SI "h_ccr_get" index))
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)
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;------------------------------------------------------------------------------
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; Misc
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(define-hardware
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(name h-fmax-compare-i-p)
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(comment "flag")
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(attrs all-fmax-isas)
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(type register USI)
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)
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;******************************************************************************
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; Operands
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;------------------------------------------------------------------------------
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; FR Registers
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(define-full-operand fmax-FRd "FRd" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ())
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(define-full-operand fmax-FRn "FRn" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ())
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(define-full-operand fmax-FRm "FRm" (all-fmax-isas (CDATA FMAX_FLOAT)) h-cr SF f-fmax-frm ((parse "fmax_cr") (print "fmax_cr")) () ())
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(define-full-operand fmax-FRd-int "FRd as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frd ((parse "fmax_cr") (print "fmax_cr")) () ())
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(define-full-operand fmax-FRn-int "FRn as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fmax-frn ((parse "fmax_cr") (print "fmax_cr")) () ())
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;------------------------------------------------------------------------------
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; Control registers
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(define-full-operand fmax-CCRn "CCRn" (all-fmax-isas (CDATA REGNUM)) h-ccr DFLT f-fmax-4-4 ((parse "fmax_ccr") (print "fmax_ccr")) () ())
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(dnop fmax-CIRR "CIRR" (all-fmax-isas SEM-ONLY) h-ccr 0)
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(dnop fmax-CBCR "CBCR" (all-fmax-isas SEM-ONLY) h-ccr 1)
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(dnop fmax-CERR "CERR" (all-fmax-isas SEM-ONLY) h-ccr 15)
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;------------------------------------------------------------------------------
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; Core General Registers
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(dnop fmax-Rm "Rm" (all-fmax-isas) h-gpr f-fmax-rm)
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;------------------------------------------------------------------------------
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; misc
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(dnop fmax-Compare-i-p "flag" (all-fmax-isas SEM-ONLY) h-fmax-compare-i-p f-nil)
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;******************************************************************************
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; Instructions
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;------------------------------------------------------------------------------
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; Binary Arithmetic
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(define-pmacro (fmax-binary-arith op opc sem)
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(dni op
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(.str op " FRd,FRn,FRm")
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(all-fmax-isas MAY_TRAP)
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(.str op " ${fmax-FRd},${fmax-FRn},${fmax-FRm}")
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(+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7) (f-fmax-16-4 0)
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fmax-FRn fmax-FRm (f-fmax-31-1 0))
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sem
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()
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)
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)
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(fmax-binary-arith fadds #x0 (set fmax-FRd (add fmax-FRn fmax-FRm)))
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(fmax-binary-arith fsubs #x1 (set fmax-FRd (sub fmax-FRn fmax-FRm)))
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(fmax-binary-arith fmuls #x2 (set fmax-FRd (mul fmax-FRn fmax-FRm)))
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(fmax-binary-arith fdivs #x3 (set fmax-FRd (div fmax-FRn fmax-FRm)))
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;------------------------------------------------------------------------------
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; Unary Arithmetic
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(define-pmacro (fmax-unary-arith op opc sem)
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(dni op
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(.str op " FRd,FRn")
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(all-fmax-isas MAY_TRAP)
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(.str op " ${fmax-FRd},${fmax-FRn}")
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(+ (f-fmax-0-4 #xF) fmax-FRd (f-fmax-8-4 opc) (f-fmax-12-4 #x7)
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(f-fmax-16-4 0) fmax-FRn (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
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sem
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()
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)
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)
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(fmax-unary-arith fsqrts #x4 (set fmax-FRd (sqrt fmax-FRn)))
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(fmax-unary-arith fabss #x5 (set fmax-FRd (abs fmax-FRn)))
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(fmax-unary-arith fnegs #x7 (set fmax-FRd (neg fmax-FRn)))
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(fmax-unary-arith fmovs #x6 (set fmax-FRd fmax-FRn))
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;------------------------------------------------------------------------------
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; Conversions
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(define-pmacro (fmax-conv op opc1 opc2 opnd1 opnd2 sem)
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(dni op
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(.str op " FRd,FRn")
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(all-fmax-isas MAY_TRAP)
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(.str op " ${" opnd1 "},${" opnd2 "}")
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(+ (f-fmax-0-4 #xF) opnd1 (f-fmax-8-4 opc1) (f-fmax-12-4 #x7)
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(f-fmax-16-4 opc2) opnd2 (f-fmax-24-4 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
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sem
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()
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)
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)
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(fmax-conv froundws #xC #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_froundws" fmax-FRn)))
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(fmax-conv ftruncws #xD #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ftruncws" fmax-FRn)))
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(fmax-conv fceilws #xE #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fceilws" fmax-FRn)))
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(fmax-conv ffloorws #xF #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ffloorws" fmax-FRn)))
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(fmax-conv fcvtws #x4 #x1 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fcvtws" fmax-FRn)))
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(fmax-conv fcvtsw #x0 #x9 fmax-FRd fmax-FRn-int (set fmax-FRd (float SF FPCONV-DEFAULT fmax-FRn-int)))
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;------------------------------------------------------------------------------
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; Comparisons
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;
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; Comparison with no exceptions
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(define-pmacro (fmax-f-sem x y) (andif (gt x y) (lt x y))) ; do this to get exception detection
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(define-pmacro (fmax-u-sem x y) (not (orif (lt x y) (orif (eq x y) (gt x y)))))
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(define-pmacro (fmax-e-sem x y) (eq x y))
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(define-pmacro (fmax-ue-sem x y) (not (orif (lt x y) (gt x y))))
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(define-pmacro (fmax-l-sem x y) (lt x y))
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(define-pmacro (fmax-ul-sem x y) (not (orif (gt x y) (eq x y))))
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(define-pmacro (fmax-le-sem x y) (orif (lt x y) (eq x y)))
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(define-pmacro (fmax-ule-sem x y) (not (gt x y)))
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(define-pmacro (fmax-comp cond suffix exceptions)
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(dni (.sym fcmp cond suffix s)
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(.str "fcmp" cond suffix "s FRn,FRm")
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;; Even though the instruction doesn't really trap if EXCEPTIONS
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;; is zero, we don't want gcc to put it in a repeat or erepeat
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;; block because of the hazards between fcmp instructions and
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;; anything that reads CBCR.
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(all-fmax-isas MAY_TRAP)
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(.str "fcmp" cond suffix "s ${fmax-FRn},${fmax-FRm}")
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(+ (f-fmax-0-4 #xF) (f-fmax-4-4 0) (.sym FMAX_ cond suffix) (f-fmax-12-4 #x7)
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(f-fmax-16-4 #x2) (f-fmax-28-1 0) fmax-FRn fmax-FRm (f-fmax-31-1 0))
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(sequence ()
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(set fmax-Compare-i-p exceptions)
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(set fmax-CBCR ((.sym fmax- cond -sem) fmax-FRn fmax-FRm))
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(set fmax-Compare-i-p 0)
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)
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()
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)
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)
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; Comparison with no exceptions
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(fmax-comp f "" 0)
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(fmax-comp u "" 0)
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(fmax-comp e "" 0)
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(fmax-comp ue "" 0)
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(fmax-comp l "" 0)
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(fmax-comp ul "" 0)
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(fmax-comp le "" 0)
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(fmax-comp ule "" 0)
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; Comparison with exceptions
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(fmax-comp f i 1)
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(fmax-comp u i 1)
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(fmax-comp e i 1)
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(fmax-comp ue i 1)
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(fmax-comp l i 1)
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(fmax-comp ul i 1)
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(fmax-comp le i 1)
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(fmax-comp ule i 1)
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;------------------------------------------------------------------------------
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; Move to/from core registers
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(dni cmov-frn-rm
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"cmov FRn,Rm"
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(all-fmax-isas (INTRINSIC "cmov1"))
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"cmov ${fmax-FRd-int},${fmax-Rm}"
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(+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
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(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
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(f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 0))
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(set fmax-FRd-int fmax-Rm)
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()
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)
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(dni cmov-rm-frn
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"cmov Rm,FRn"
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(all-fmax-isas (INTRINSIC "cmov2"))
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"cmov ${fmax-Rm},${fmax-FRd-int}"
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(+ (f-fmax-0-4 #xF) fmax-FRd-int fmax-Rm (f-fmax-12-4 #x7)
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(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
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(f-fmax-29-1 0) (f-fmax-30-1 0) (f-fmax-31-1 1))
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(set fmax-Rm fmax-FRd-int)
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()
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)
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(dni cmovc-ccrn-rm
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"cmovc CCRn,Rm"
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(all-fmax-isas (INTRINSIC "cmovc1"))
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"cmovc ${fmax-CCRn},${fmax-Rm}"
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(+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7)
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(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
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(f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 0))
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(set fmax-CCRn fmax-Rm)
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()
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)
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(dni cmovc-rm-ccrn
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"cmovc Rm,CCRn"
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(all-fmax-isas (INTRINSIC "cmovc2"))
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"cmovc ${fmax-Rm},${fmax-CCRn}"
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(+ (f-fmax-0-4 #xF) fmax-CCRn fmax-Rm (f-fmax-12-4 #x7)
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(f-fmax-16-4 #xF) (f-fmax-20-4 0) (f-fmax-24-4 0)
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(f-fmax-28-1 0) (f-fmax-29-1 0) (f-fmax-30-1 1) (f-fmax-31-1 1))
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(set fmax-Rm fmax-CCRn)
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()
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)
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