Projet_SETI_RISC-V/neorv32/docs/userguide/content.adoc
2023-03-06 14:48:14 +01:00

75 lines
2.9 KiB
Text

Let's Get It Started!
This user guide uses the NEORV32 project _as is_ from the official `neorv32` repository.
To make your first NEORV32 project run, follow the guides from the upcoming sections. It is recommended to
follow these guides step by step and eventually in the presented order.
[TIP]
This guide uses the minimalistic and platform/toolchain agnostic SoC **test setups** from
`rtl/test_setups` for illustration. You can use one of the provided test setups for
your first FPGA tests. +
+
For more sophisticated example setups have a look at the
https://github.com/stnolting/neorv32-setups[neorv32-setups] repository,
which provides **SoC setups** for various FPGAs, boards and toolchains.
**Quick Links**
* <<_software_toolchain_setup, Toolchain>>, <<_general_hardware_setup, hardware>> and <<_general_software_framework_setup, general software framework>> setup
* <<_application_program_compilation, compile>> an application and <<_uploading_and_starting_of_a_binary_executable_image_via_uart, upload>> it or making it
<<_installing_an_executable_directly_into_memory, persistent>> in internal memory
* setup a new <<_setup_of_a_new_application_program_project, application project>>
* configure <<_enabling_risc_v_cpu_extensions, RISC-V ISA extensions>> and <<_application_specific_processor_configuration, optimizing>> the core for your application
* add <<_adding_custom_hardware_modules, custom hardware extensions>> and <<_customizing_the_internal_bootloader, customizing the bootloader>>
* <<_programming_an_external_spi_flash_via_the_bootloader, program>> an external SPI flash for persistent application storage
* generate a Xilinx Vivado <<_packaging_the_processor_as_ip_block_for_xilinx_vivado_block_designer, IP block>>
* <<_simulating_the_processor, simulate>> the processor and <<_building_the_documentation, build the documentation>>
* RTOS support for <<_zephyr_rtos_support, Zephyr>> and <<_freertos_support, FreeRTOS>>
* build SoCs using <<_litex_soc_builder_support, LiteX>>
* in-system <<_debugging_using_the_on_chip_debugger, debugging>> of the whole processor
* <<_neorv32_in_verilog>> - an all-Verilog "version" of the processor
include::sw_toolchain_setup.adoc[]
include::general_hw_setup.adoc[]
include::general_sw_framework_setup.adoc[]
include::application_program_compilation.adoc[]
include::executable_upload.adoc[]
include::installing_an_executable.adoc[]
include::new_application_project.adoc[]
include::enabling_riscv_extensions.adoc[]
include::application_specific_configuration.adoc[]
include::adding_custom_hw_modules.adoc[]
include::customizing_the_bootloader.adoc[]
include::programming_an_external_spi_flash_via_bootloader.adoc[]
include::packaging_vivado.adoc[]
include::simulating_the_processor.adoc[]
include::building_the_documentation.adoc[]
include::zephyr_support.adoc[]
include::free_rtos_support.adoc[]
include::litex_support.adoc[]
include::debugging_with_ocd.adoc[]
include::neorv32_in_verilog.adoc[]
include::../legal.adoc[]