277 lines
9.2 KiB
C
277 lines
9.2 KiB
C
/*
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* HPPA interrupt helper routines
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*
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* Copyright (c) 2017 Richard Henderson
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "hw/core/cpu.h"
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#include "hw/hppa/hppa_hardware.h"
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#ifndef CONFIG_USER_ONLY
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static void eval_interrupt(HPPACPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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if (cpu->env.cr[CR_EIRR] & cpu->env.cr[CR_EIEM]) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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/* Each CPU has a word mapped into the GSC bus. Anything on the GSC bus
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* can write to this word to raise an external interrupt on the target CPU.
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* This includes the system controler (DINO) for regular devices, or
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* another CPU for SMP interprocessor interrupts.
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*/
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static uint64_t io_eir_read(void *opaque, hwaddr addr, unsigned size)
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{
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HPPACPU *cpu = opaque;
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/* ??? What does a read of this register over the GSC bus do? */
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return cpu->env.cr[CR_EIRR];
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}
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static void io_eir_write(void *opaque, hwaddr addr,
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uint64_t data, unsigned size)
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{
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HPPACPU *cpu = opaque;
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int le_bit = ~data & (TARGET_REGISTER_BITS - 1);
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cpu->env.cr[CR_EIRR] |= (target_ureg)1 << le_bit;
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eval_interrupt(cpu);
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}
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const MemoryRegionOps hppa_io_eir_ops = {
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.read = io_eir_read,
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.write = io_eir_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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void hppa_cpu_alarm_timer(void *opaque)
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{
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/* Raise interrupt 0. */
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io_eir_write(opaque, 0, 0, 4);
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}
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void HELPER(write_eirr)(CPUHPPAState *env, target_ureg val)
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{
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env->cr[CR_EIRR] &= ~val;
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qemu_mutex_lock_iothread();
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eval_interrupt(env_archcpu(env));
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qemu_mutex_unlock_iothread();
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}
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void HELPER(write_eiem)(CPUHPPAState *env, target_ureg val)
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{
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env->cr[CR_EIEM] = val;
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qemu_mutex_lock_iothread();
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eval_interrupt(env_archcpu(env));
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qemu_mutex_unlock_iothread();
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}
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void hppa_cpu_do_interrupt(CPUState *cs)
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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CPUHPPAState *env = &cpu->env;
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int i = cs->exception_index;
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target_ureg iaoq_f = env->iaoq_f;
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target_ureg iaoq_b = env->iaoq_b;
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uint64_t iasq_f = env->iasq_f;
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uint64_t iasq_b = env->iasq_b;
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target_ureg old_psw;
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/* As documented in pa2.0 -- interruption handling. */
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/* step 1 */
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env->cr[CR_IPSW] = old_psw = cpu_hppa_get_psw(env);
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/* step 2 -- note PSW_W == 0 for !HPPA64. */
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cpu_hppa_put_psw(env, PSW_W | (i == EXCP_HPMC ? PSW_M : 0));
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/* step 3 */
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env->cr[CR_IIASQ] = iasq_f >> 32;
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env->cr_back[0] = iasq_b >> 32;
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env->cr[CR_IIAOQ] = iaoq_f;
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env->cr_back[1] = iaoq_b;
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if (old_psw & PSW_Q) {
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/* step 5 */
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/* ISR and IOR will be set elsewhere. */
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switch (i) {
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case EXCP_ILL:
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case EXCP_BREAK:
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case EXCP_PRIV_REG:
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case EXCP_PRIV_OPR:
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/* IIR set via translate.c. */
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break;
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case EXCP_OVERFLOW:
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case EXCP_COND:
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case EXCP_ASSIST:
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case EXCP_DTLB_MISS:
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case EXCP_NA_ITLB_MISS:
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case EXCP_NA_DTLB_MISS:
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case EXCP_DMAR:
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case EXCP_DMPI:
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case EXCP_UNALIGN:
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case EXCP_DMP:
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case EXCP_DMB:
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case EXCP_TLB_DIRTY:
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case EXCP_PAGE_REF:
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case EXCP_ASSIST_EMU:
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{
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/* Avoid reading directly from the virtual address, lest we
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raise another exception from some sort of TLB issue. */
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/* ??? An alternate fool-proof method would be to store the
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instruction data into the unwind info. That's probably
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a bit too much in the way of extra storage required. */
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vaddr vaddr;
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hwaddr paddr;
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paddr = vaddr = iaoq_f & -4;
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if (old_psw & PSW_C) {
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int prot, t;
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vaddr = hppa_form_gva_psw(old_psw, iasq_f, vaddr);
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t = hppa_get_physical_address(env, vaddr, MMU_KERNEL_IDX,
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0, &paddr, &prot);
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if (t >= 0) {
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/* We can't re-load the instruction. */
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env->cr[CR_IIR] = 0;
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break;
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}
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}
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env->cr[CR_IIR] = ldl_phys(cs->as, paddr);
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}
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break;
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default:
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/* Other exceptions do not set IIR. */
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break;
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}
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/* step 6 */
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env->shadow[0] = env->gr[1];
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env->shadow[1] = env->gr[8];
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env->shadow[2] = env->gr[9];
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env->shadow[3] = env->gr[16];
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env->shadow[4] = env->gr[17];
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env->shadow[5] = env->gr[24];
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env->shadow[6] = env->gr[25];
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}
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/* step 7 */
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if (i == EXCP_TOC) {
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env->iaoq_f = FIRMWARE_START;
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/* help SeaBIOS and provide iaoq_b and iasq_back in shadow regs */
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env->gr[24] = env->cr_back[0];
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env->gr[25] = env->cr_back[1];
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} else {
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env->iaoq_f = env->cr[CR_IVA] + 32 * i;
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}
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env->iaoq_b = env->iaoq_f + 4;
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env->iasq_f = 0;
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env->iasq_b = 0;
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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static const char * const names[] = {
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[EXCP_HPMC] = "high priority machine check",
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[EXCP_POWER_FAIL] = "power fail interrupt",
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[EXCP_RC] = "recovery counter trap",
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[EXCP_EXT_INTERRUPT] = "external interrupt",
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[EXCP_LPMC] = "low priority machine check",
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[EXCP_ITLB_MISS] = "instruction tlb miss fault",
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[EXCP_IMP] = "instruction memory protection trap",
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[EXCP_ILL] = "illegal instruction trap",
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[EXCP_BREAK] = "break instruction trap",
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[EXCP_PRIV_OPR] = "privileged operation trap",
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[EXCP_PRIV_REG] = "privileged register trap",
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[EXCP_OVERFLOW] = "overflow trap",
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[EXCP_COND] = "conditional trap",
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[EXCP_ASSIST] = "assist exception trap",
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[EXCP_DTLB_MISS] = "data tlb miss fault",
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[EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss",
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[EXCP_NA_DTLB_MISS] = "non-access data tlb miss",
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[EXCP_DMP] = "data memory protection trap",
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[EXCP_DMB] = "data memory break trap",
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[EXCP_TLB_DIRTY] = "tlb dirty bit trap",
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[EXCP_PAGE_REF] = "page reference trap",
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[EXCP_ASSIST_EMU] = "assist emulation trap",
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[EXCP_HPT] = "high-privilege transfer trap",
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[EXCP_LPT] = "low-privilege transfer trap",
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[EXCP_TB] = "taken branch trap",
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[EXCP_DMAR] = "data memory access rights trap",
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[EXCP_DMPI] = "data memory protection id trap",
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[EXCP_UNALIGN] = "unaligned data reference trap",
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[EXCP_PER_INTERRUPT] = "performance monitor interrupt",
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[EXCP_SYSCALL] = "syscall",
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[EXCP_SYSCALL_LWS] = "syscall-lws",
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[EXCP_TOC] = "TOC (transfer of control)",
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};
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static int count;
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const char *name = NULL;
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char unknown[16];
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if (i >= 0 && i < ARRAY_SIZE(names)) {
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name = names[i];
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}
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if (!name) {
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snprintf(unknown, sizeof(unknown), "unknown %d", i);
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name = unknown;
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}
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qemu_log("INT %6d: %s @ " TARGET_FMT_lx "," TARGET_FMT_lx
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" -> " TREG_FMT_lx " " TARGET_FMT_lx "\n",
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++count, name,
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hppa_form_gva(env, iasq_f, iaoq_f),
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hppa_form_gva(env, iasq_b, iaoq_b),
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env->iaoq_f,
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hppa_form_gva(env, (uint64_t)env->cr[CR_ISR] << 32,
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env->cr[CR_IOR]));
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}
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cs->exception_index = -1;
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}
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bool hppa_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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HPPACPU *cpu = HPPA_CPU(cs);
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CPUHPPAState *env = &cpu->env;
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if (interrupt_request & CPU_INTERRUPT_NMI) {
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/* Raise TOC (NMI) interrupt */
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cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI);
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cs->exception_index = EXCP_TOC;
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hppa_cpu_do_interrupt(cs);
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return true;
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}
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/* If interrupts are requested and enabled, raise them. */
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if ((env->psw & PSW_I) && (interrupt_request & CPU_INTERRUPT_HARD)) {
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cs->exception_index = EXCP_EXT_INTERRUPT;
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hppa_cpu_do_interrupt(cs);
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return true;
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}
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return false;
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}
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#endif /* !CONFIG_USER_ONLY */
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