361 lines
5.3 KiB
PHP
361 lines
5.3 KiB
PHP
; Copied from fr30 and modified.
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; r9, r11-r13 are used as tmps, consider them call clobbered by these macros.
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;
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; Do not use the macro counter \@ in macros, there's a bug in
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; gas 2.9.1 when it is also a line-separator.
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;
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; Don't require the $-prefix on registers.
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.syntax no_register_prefix
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.macro startnostack
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.data
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.space 64,0 ; Simple stack
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stackhi:
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failmsg:
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.ascii "fail\n"
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passmsg:
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.ascii "pass\n"
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.text
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break 11
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.global _start
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_start:
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.endm
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.macro start
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startnostack
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move.d stackhi,sp
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.endm
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; Exit with return code
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.macro exit rc
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move.d \rc,r10
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moveq 1,r9 ; == __NR_exit
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break 13
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break 15
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.endm
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; Pass the test case
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.macro pass
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moveq 5,r12
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move.d passmsg,r11
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move.d 1,r10
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moveq 4,r9 ; == __NR_write
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break 13
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exit 0
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.endm
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; Fail the testcase
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.macro fail
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; moveq 5,r12
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; move.d failmsg,r11
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; move.d 1,r10
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; moveq 4,r1
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; break 13
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; exit 1
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break 15
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.endm
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.macro quit
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break 15
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.endm
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.macro dumpr3
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break 14
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.endm
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; Load an immediate value into a general register
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; TODO: use minimal sized insn
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.macro mvi_h_gr val reg
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move.d \val,\reg
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.endm
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; Load an immediate value into a dedicated register
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.macro mvi_h_dr val reg
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move.d \val,r9
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move.d r9,\reg
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.endm
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; Load a general register into another general register
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.macro mvr_h_gr src targ
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move.d \src,\targ
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.endm
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; Store an immediate into a word in memory
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.macro mvi_h_mem val addr
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mvi_h_gr \val r11
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mvr_h_mem r11,\addr
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.endm
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; Store a register into a word in memory
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.macro mvr_h_mem reg addr
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move.d \addr,$r13
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move.d \reg,[$r13]
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.endm
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; Store the current ps on the stack
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.macro save_ps
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.if ..asm.arch.cris.v32
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move ccs,acr ; Push will do a "subq" first.
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push acr
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.else
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push dccr
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.endif
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.endm
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; Load a word value from memory
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.macro ldmem_h_gr addr reg
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move.d \addr,$r13
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move.d [$r13],\reg
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.endm
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; Add 2 general registers
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.macro add_h_gr reg1 reg2
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add.d \reg1,\reg2
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.endm
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; Increment a register by and immediate
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.macro inci_h_gr inc reg
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mvi_h_gr \inc,r11
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add.d r11,\reg
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.endm
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; Test the value of an immediate against a general register
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.macro test_h_gr val reg
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cmp.d \val,\reg
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beq 9f
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nop
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fail
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9:
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.endm
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; compare two general registers
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.macro testr_h_gr reg1 reg2
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cmp.d \reg1,\reg2
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beq 9f
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fail
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9:
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.endm
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; Test the value of an immediate against a dedicated register
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.macro test_h_dr val reg
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move \reg,$r12
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test_h_gr \val $r12
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.endm
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; Test the value of an general register against a dedicated register
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.macro testr_h_dr gr dr
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move \dr,$r12
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testr_h_gr \gr $r12
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.endm
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; Compare an immediate with word in memory
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.macro test_h_mem val addr
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ldmem_h_gr \addr $r12
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test_h_gr \val $r12
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.endm
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; Compare a general register with word in memory
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.macro testr_h_mem reg addr
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ldmem_h_gr \addr r12
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testr_h_gr \reg r12
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.endm
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; Set the condition codes
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; The lower bits of the mask *are* nzvc, so we don't
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; have to do anything strange.
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.macro set_cc mask
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move.w \mask,r13
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.if ..asm.arch.cris.v32
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move r13,ccs
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.else
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move r13,ccr
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.endif
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.endm
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; Set the stack mode
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; .macro set_s_user
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; orccr 0x20
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; .endm
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;
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; .macro set_s_system
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; andccr 0x1f
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; .endm
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;
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;; Test the stack mode
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; .macro test_s_user
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; mvr_h_gr ps,r9
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; mvi_h_gr 0x20,r11
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; and r11,r9
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; test_h_gr 0x20,r9
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; .endm
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;
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; .macro test_s_system
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; mvr_h_gr ps,r9
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; mvi_h_gr 0x20,r11
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; and r11,r9
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; test_h_gr 0x0,r9
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; .endm
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; Set the interrupt bit
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; ??? Do they mean "enable interrupts" or "disable interrupts"?
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; Assuming enable here.
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.macro set_i val
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.if (\val == 1)
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ei
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.else
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di
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.endif
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.endm
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; Test the stack mode
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; .macro test_i val
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; mvr_h_gr ps,r9
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; mvi_h_gr 0x10,r11
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; and r11,r9
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; .if (\val == 1)
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; test_h_gr 0x10,r9
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; .else
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; test_h_gr 0x0,r9
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; .endif
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; .endm
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;
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;; Set the ilm
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; .macro set_ilm val
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; stilm \val
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; .endm
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;
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;; Test the ilm
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; .macro test_ilm val
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; mvr_h_gr ps,r9
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; mvi_h_gr 0x1f0000,r11
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; and r11,r9
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; mvi_h_gr \val,r12
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; mvi_h_gr 0x1f,r11
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; and r11,r12
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; lsl 15,r12
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; lsl 1,r12
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; testr_h_gr r9,r12
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; .endm
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;
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; Test the condition codes
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.macro test_cc N Z V C
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.if \N
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bpl 9f
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nop
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.else
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bmi 9f
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nop
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.endif
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.if \Z
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bne 9f
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nop
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.else
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beq 9f
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nop
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.endif
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.if \V
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bvc 9f
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nop
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.else
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bvs 9f
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nop
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.endif
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.if \C
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bcc 9f
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nop
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.else
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bcs 9f
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nop
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.endif
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ba 8f
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nop
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9:
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fail
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8:
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.endm
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.macro test_move_cc N Z V C
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.if ..asm.arch.cris.v32
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; V and C aren't affected on v32, so to re-use the test-cases,
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; we fake them cleared. There's a separate test, nonvcv32.ms
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; covering this omission.
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clearf vc
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test_cc \N \Z 0 0
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.else
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test_cc \N \Z \V \C
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.endif
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.endm
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; Set the division bits
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; .macro set_dbits val
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; mvr_h_gr ps,r12
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; mvi_h_gr 0xfffff8ff,r11
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; and r11,r12
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; mvi_h_gr \val,r9
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; mvi_h_gr 3,r11
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; and r11,r9
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; lsl 9,r9
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; or r9,r12
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; mvr_h_gr r12,ps
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; .endm
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;
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;; Test the division bits
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; .macro test_dbits val
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; mvr_h_gr ps,r9
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; lsr 9,r9
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; mvi_h_gr 3,r11
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; and r11,r9
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; test_h_gr \val,r9
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; .endm
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;
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; Save the return pointer
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.macro save_rp
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push srp
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.ENDM
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; restore the return pointer
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.macro restore_rp
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pop srp
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.endm
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; Ensure branch taken
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.macro take_branch opcode
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\opcode 9f
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nop
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fail
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9:
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.endm
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.macro take_branch_d opcode val
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\opcode 9f
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nop
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move.d \val,r9
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fail
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9:
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test_h_gr \val,r9
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.endm
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; Ensure branch not taken
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.macro no_branch opcode
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\opcode 9f
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nop
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ba 8f
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nop
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9:
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fail
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8:
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.endm
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.macro no_branch_d opcode val
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\opcode 9f
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move.d \val,r9
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nop
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ba 8f
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nop
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9:
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fail
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8:
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test_h_gr \val,r9
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.endm
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