Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/cris/asm/raw11.ms
2023-03-06 14:48:14 +01:00

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; Checking read-after-write: swrite-then-nop-read 2 cycles.
#mach: crisv32
#output: Basic clock cycles, total @: 5\n
#output: Memory source stall cycles: 0\n
#output: Memory read-after-write stall cycles: 2\n
#output: Movem source stall cycles: 0\n
#output: Movem destination stall cycles: 0\n
#output: Movem address stall cycles: 0\n
#output: Multiplication source stall cycles: 0\n
#output: Jump source stall cycles: 0\n
#output: Branch misprediction stall cycles: 0\n
#output: Jump target stall cycles: 0\n
#sim: --cris-cycles=basic
.include "testutils.inc"
startnostack
.lcomm x,4
.lcomm y,4
move.d x,$r0
move.d y,$r1
clear.d [$r0]
nop
move [$r1],$srp
break 15