208 lines
7 KiB
C
208 lines
7 KiB
C
/* Target dependent code for ARC architecture, for GDB.
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Copyright 2005-2022 Free Software Foundation, Inc.
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Contributed by Synopsys Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef ARC_TDEP_H
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#define ARC_TDEP_H
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/* Need disassemble_info. */
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#include "dis-asm.h"
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#include "gdbarch.h"
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#include "arch/arc.h"
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/* To simplify GDB code this enum assumes that internal regnums should be same
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as architectural register numbers, i.e. PCL regnum is 63. This allows to
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use internal GDB regnums as architectural numbers when dealing with
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instruction encodings, for example when analyzing what are the registers
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saved in function prologue. */
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enum arc_regnum
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{
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/* Core registers. */
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ARC_R0_REGNUM = 0,
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ARC_R1_REGNUM = 1,
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ARC_R4_REGNUM = 4,
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ARC_R7_REGNUM = 7,
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ARC_R9_REGNUM = 9,
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ARC_R13_REGNUM = 13,
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ARC_R16_REGNUM = 16,
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ARC_R25_REGNUM = 25,
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/* Global data pointer. */
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ARC_GP_REGNUM,
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/* Frame pointer. */
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ARC_FP_REGNUM,
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/* Stack pointer. */
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ARC_SP_REGNUM,
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/* Return address from interrupt. */
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ARC_ILINK_REGNUM,
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ARC_R30_REGNUM,
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/* Return address from function. */
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ARC_BLINK_REGNUM,
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/* Accumulator registers. */
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ARC_R58_REGNUM = 58,
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ARC_R59_REGNUM,
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/* Zero-delay loop counter. */
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ARC_LP_COUNT_REGNUM = 60,
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/* Reserved register number. There should never be a register with such
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number, this name is needed only for a sanity check in
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arc_cannot_(fetch|store)_register. */
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ARC_RESERVED_REGNUM,
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/* Long-immediate value. This is not a physical register - if instruction
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has register 62 as an operand, then this operand is a literal value
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stored in the instruction memory right after the instruction itself.
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This value is required in this enumeration as an architectural number
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for instruction analysis. */
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ARC_LIMM_REGNUM,
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/* Program counter, aligned to 4-bytes, read-only. */
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ARC_PCL_REGNUM,
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ARC_LAST_CORE_REGNUM = ARC_PCL_REGNUM,
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/* AUX registers. */
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/* Actual program counter. */
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ARC_PC_REGNUM,
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ARC_FIRST_AUX_REGNUM = ARC_PC_REGNUM,
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/* Status register. */
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ARC_STATUS32_REGNUM,
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/* Zero-delay loop start instruction. */
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ARC_LP_START_REGNUM,
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/* Zero-delay loop next-after-last instruction. */
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ARC_LP_END_REGNUM,
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/* Branch target address. */
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ARC_BTA_REGNUM,
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/* Exception return address. */
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ARC_ERET_REGNUM,
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ARC_LAST_AUX_REGNUM = ARC_ERET_REGNUM,
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ARC_LAST_REGNUM = ARC_LAST_AUX_REGNUM,
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/* Additional ABI constants. */
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ARC_FIRST_ARG_REGNUM = ARC_R0_REGNUM,
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ARC_LAST_ARG_REGNUM = ARC_R7_REGNUM,
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ARC_FIRST_CALLEE_SAVED_REGNUM = ARC_R13_REGNUM,
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ARC_LAST_CALLEE_SAVED_REGNUM = ARC_R25_REGNUM,
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};
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/* Number of bytes in ARC register. All ARC registers are considered 32-bit.
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Those registers, which are actually shorter has zero-on-read for extra bits.
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Longer registers are represented as pairs of 32-bit registers. */
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#define ARC_REGISTER_SIZE 4
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/* STATUS32 register: hardware loops disabled bit. */
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#define ARC_STATUS32_L_MASK (1 << 12)
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/* STATUS32 register: current instruction is a delay slot. */
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#define ARC_STATUS32_DE_MASK (1 << 6)
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/* Special value for register offset arrays. */
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#define ARC_OFFSET_NO_REGISTER (-1)
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#define arc_print(fmt, args...) gdb_printf (gdb_stdlog, fmt, ##args)
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extern bool arc_debug;
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/* Print an "arc" debug statement. */
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#define arc_debug_printf(fmt, ...) \
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debug_prefixed_printf_cond (arc_debug, "arc", fmt, ##__VA_ARGS__)
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/* Target-dependent information. */
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struct arc_gdbarch_tdep : gdbarch_tdep
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{
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/* Offset to PC value in jump buffer. If this is negative, longjmp
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support will be disabled. */
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int jb_pc = 0;
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/* Whether target has hardware (aka zero-delay) loops. */
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bool has_hw_loops = false;
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/* Detect sigtramp. */
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bool (*is_sigtramp) (struct frame_info *) = nullptr;
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/* Get address of sigcontext for sigtramp. */
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CORE_ADDR (*sigcontext_addr) (struct frame_info *) = nullptr;
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/* Offset of registers in `struct sigcontext'. */
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const int *sc_reg_offset = nullptr;
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/* Number of registers in sc_reg_offsets. Most likely a ARC_LAST_REGNUM,
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but in theory it could be less, so it is kept separate. */
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int sc_num_regs = 0;
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};
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/* Utility functions used by other ARC-specific modules. */
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static inline int
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arc_mach_is_arc600 (struct gdbarch *gdbarch)
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{
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return (gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc600
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|| gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc601);
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}
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static inline int
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arc_mach_is_arc700 (struct gdbarch *gdbarch)
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{
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return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arc700;
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}
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static inline int
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arc_mach_is_arcv2 (struct gdbarch *gdbarch)
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{
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return gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_arc_arcv2;
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}
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/* ARC EM and ARC HS are unique BFD arches, however they share the same machine
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number as "ARCv2". */
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static inline bool
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arc_arch_is_hs (const struct bfd_arch_info* arch)
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{
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return startswith (arch->printable_name, "HS");
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}
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static inline bool
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arc_arch_is_em (const struct bfd_arch_info* arch)
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{
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return startswith (arch->printable_name, "EM");
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}
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/* Function to access ARC disassembler. Underlying opcodes disassembler will
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print an instruction into stream specified in the INFO, so if it is
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undesired, then this stream should be set to some invisible stream, but it
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can't be set to an actual NULL value - that would cause a crash. */
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int arc_delayed_print_insn (bfd_vma addr, struct disassemble_info *info);
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/* Get branch/jump target address for the INSN. Note that this function
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returns branch target and doesn't evaluate if this branch is taken or not.
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For the indirect jumps value depends in register state, hence can change.
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It is an error to call this function for a non-branch instruction. */
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CORE_ADDR arc_insn_get_branch_target (const struct arc_instruction &insn);
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/* Get address of next instruction after INSN, assuming linear execution (no
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taken branches). If instruction has a delay slot, then returned value will
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point at the instruction in delay slot. That is - "address of instruction +
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instruction length with LIMM". */
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CORE_ADDR arc_insn_get_linear_next_pc (const struct arc_instruction &insn);
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/* Create an arc_arch_features instance from the provided data. */
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arc_arch_features arc_arch_features_create (const bfd *abfd,
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const unsigned long mach);
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#endif /* ARC_TDEP_H */
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