192 lines
5.2 KiB
ArmAsm
192 lines
5.2 KiB
ArmAsm
# EPIPHANY implementation of wrappers over user C ISR ()
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# Copyright (c) 2011, Adapteva, Inc.
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# All rights reserved.
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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# * Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution.
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# * Neither the name of Adapteva nor the names of its contributors may be
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# used to endorse or promote products derived from this software without
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# specific prior written permission.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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.section RESERVED_CRT0,"a",@progbits ;
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.set sw_exception_v_n, 1
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.set page_miss_v_n, 2
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.set timer0_expired_v_n, 3;
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.set timer1_expired_v_n, 4;
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.set message_v_n, 5;
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.set dma0_v_n, 6;
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.set dma1_v_n, 7;
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.set wand_v_n, 8;
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.set soft_v_n, 9
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// preserve isr-mods to ACTIVE, GID, KERNEL, WAND, & EXCAUSE bits in the status reg
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.set status_mask, 0x0007000f;
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// for the wand isr, preserve isr-mods to ACTIVE, GID, KERNEL, & EXCAUSE, but
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// clear the WAND bit.
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.set wand_status_mask, 0x00070007;
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//IVT wrappers
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.global _DEFAULT_ISR_CALLBACK;
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.balign 4
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.type _DEFAULT_ISR_CALLBACK, %function
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_DEFAULT_ISR_CALLBACK:
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rts
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.size _DEFAULT_ISR_CALLBACK, .-_DEFAULT_ISR_CALLBACK
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.global _DEFAULT_ISR_CALLBACK_FOR_sw_exception_v;
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.balign 4
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.type _DEFAULT_ISR_CALLBACK_FOR_sw_exception_v, %function
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_DEFAULT_ISR_CALLBACK_FOR_sw_exception_v:
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trap 5;; FAIL
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.size _DEFAULT_ISR_CALLBACK_FOR_sw_exception_v, .-_DEFAULT_ISR_CALLBACK_FOR_sw_exception_v
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.set NUMBER_ENTRIES_IN_IVT, 8
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.global _ISR_VECTOR;
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.balign 4
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.type _ISR_VECTOR, %object
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_ISR_VECTOR:
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.word _DEFAULT_ISR_CALLBACK_FOR_sw_exception_v; reset
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.word _DEFAULT_ISR_CALLBACK_FOR_sw_exception_v; sw_exception
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.word _DEFAULT_ISR_CALLBACK_FOR_sw_exception_v; page_miss
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.rept NUMBER_ENTRIES_IN_IVT
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.word _DEFAULT_ISR_CALLBACK
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.endr
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.size _ISR_VECTOR, .-_ISR_VECTOR
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.macro IVT_ENTRY_CALL entry_v_
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;; assuming we have valid frame poiter
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str fp, [sp],-0x10
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str r0, [sp,+0xf]
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str r1, [sp,+0xe]
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mov r0, \entry_v_
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.if \entry_v_ == wand_v_n
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mov r1, %low(wand_status_mask) ; this mask will exclude WAND, so it will
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movt r1, %high(wand_status_mask) ; be forcibly cleared
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.else
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mov r1, %low(status_mask)
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movt r1, %high(status_mask)
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.endif
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str r1, [sp,0x9] ; save the status register isr-preserve mask on the stack
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b __dispatcher
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.endm
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.global __dispatcher;
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.balign 4
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.type __dispatcher, %function
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__dispatcher:
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str lr, [sp,+0xd]
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movfs.l r1,status
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str r1, [sp,+0xc]
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movfs.l r1,iret
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str r1, [sp,+0xb]
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str r2, [sp,+0xa]
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str r3, [sp,+0x8]
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mov fp,sp
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//TODO allow nesting
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//gie
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lsl r2, r0, 2
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mov r1, %low(_ISR_VECTOR)
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add r2, r2, r1
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ldr r1, [r2,0] ;; r1 = _ISR_VECTOR[entry_v]
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mov r2, 3
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add r0, r0, r2 ;; r0 = signum
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jalr r1
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mov sp,fp
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//gid
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// preserve isr-modifications to some of the bits in the status register,
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// but restore the rest to pre-interrupt values.
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// status = (status[post_isr] & status_mask) | (status[pre_isr] & ~status_mask)
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ldr.l r2, [sp, 9] ; fetch the status register isr preserve mask from the stack
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movfs r1, status
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and r1, r1, r2; (status[post_isr] & status_mask)
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ldr r0, [sp,+0xc]
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mov r2, %low(~status_mask)
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movt r2, %high(~status_mask)
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and r0, r0, r2; (status[pre_isr] & ~status_mask)
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orr r0, r0, r1 ; combine pre_isr & post_isr status bits
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movts.l status, r0
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ldr r0, [sp,+0xb]
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movts.l iret,r0
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ldr lr,[sp,+0xd];
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ldr r1,[sp,+0xe]
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ldr r0,[sp,+0xf]
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ldr r2,[sp,+0xa]
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ldr r3,[sp,+0x8]
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ldr fp,[sp],+0x10
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ldr fp,[sp,0]
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rti
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.size __dispatcher, .-__dispatcher
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.global .sw_exception_v;
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.type .sw_exception_v, %function
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.sw_exception_v:
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IVT_ENTRY_CALL sw_exception_v_n;
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.size .sw_exception_v, .-.sw_exception_v
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.global .page_miss_v;
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.type .page_miss_v, %function
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.page_miss_v:
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IVT_ENTRY_CALL page_miss_v_n;
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.size .page_miss_v, .-.page_miss_v
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.global .timer0_expired_v;
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.timer0_expired_v:
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IVT_ENTRY_CALL timer0_expired_v_n;
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.global .timer1_expired_v;
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.timer1_expired_v:
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IVT_ENTRY_CALL timer1_expired_v_n;
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.global .message_v;
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.message_v:
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IVT_ENTRY_CALL message_v_n;
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.global .dma0_v;
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.dma0_v:
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IVT_ENTRY_CALL dma0_v_n;
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.global .dma1_v;
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.dma1_v:
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IVT_ENTRY_CALL dma1_v_n;
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.global .wand_v;
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.wand_v:
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IVT_ENTRY_CALL wand_v_n;
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.global .soft_v;
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.soft_v:
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IVT_ENTRY_CALL soft_v_n;
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