Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/m32r/stb-d.cgs
2023-03-06 14:48:14 +01:00

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# m32r testcase for stb $src1,@($slo16,$src2)
# mach(): m32r m32rx
.include "testutils.inc"
start
.global stb_d
stb_d:
mvaddr_h_gr r4, data_loc
mvi_h_gr r5, 0x1234
stb r5, @(#8,r4)
mvaddr_h_gr r4, data_loc2
ld r4, @r4
test_h_gr r4, 0x34000000 ; big endian processor
pass
data_loc:
.word 0
.word 0
data_loc2:
.word 0