Projet_SETI_RISC-V/riscv-gnu-toolchain/binutils/sim/testsuite/arm/thumb/ldr-sprel.cgs
2023-03-06 14:48:14 +01:00

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Text

# arm testcase for ldr ${bit10-rd},[sp,#$word8]
# mach: unfinished
.include "testutils.inc"
start
.global ldr_sprel
ldr_sprel:
ldr r0,[sp,#0]
pass