Projet_SETI_RISC-V/neorv32/sim
2023-03-06 14:48:14 +01:00
..
simple projet 2023-03-06 14:48:14 +01:00
neorv32_tb.vhd projet 2023-03-06 14:48:14 +01:00
README.md projet 2023-03-06 14:48:14 +01:00
run.py projet 2023-03-06 14:48:14 +01:00
uart_rx.vhd projet 2023-03-06 14:48:14 +01:00
uart_rx_pkg.vhd projet 2023-03-06 14:48:14 +01:00

Simulation Sources

simple

Simple testbench for the NEORV32 Processor and script for simulation using GHDL.

VUnit testbench

VUnit testbench for the NEORV32 Processor.