126 lines
5.4 KiB
Text
126 lines
5.4 KiB
Text
<<<
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:sectnums:
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== Legal
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// ####################################################################################################################
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=== License
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**BSD 3-Clause License**
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Copyright (c) 2023, Stephan Nolting. All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that
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the following conditions are met:
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. Redistributions of source code must retain the above copyright notice, this list of conditions and the
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following disclaimer.
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. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and
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the following disclaimer in the documentation and/or other materials provided with the distribution.
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. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or
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promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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OF THE POSSIBILITY OF SUCH DAMAGE.
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==========================
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**The NEORV32 RISC-V Processor** +
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HQ: https://github.com/stnolting/neorv32 +
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By Dipl.-Ing. (M.Sc.) Stephan Nolting +
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European Union, Germany +
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Contact: stnolting@gmail.com
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==========================
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<<<
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// ####################################################################################################################
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:sectnums!:
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=== Proprietary Notice
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* "GitHub" is a Subsidiary of Microsoft Corporation.
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* "Vivado" and "Artix" are trademarks of Xilinx Inc.
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* "AXI", "AXI4-Lite" and "AXI4-Stream" are trademarks of Arm Holdings plc.
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* "ModelSim" is a trademark of Mentor Graphics – A Siemens Business.
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* "Quartus Prime" and "Cyclone" are trademarks of Intel Corporation.
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* "iCE40", "UltraPlus" and "Radiant" are trademarks of Lattice Semiconductor Corporation.
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* "Windows" is a trademark of Microsoft Corporation.
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* "Tera Term" copyright by T. Teranishi.
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* "NeoPixel" is a trademark of Adafruit Industries.
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* Images/figures made with _Microsoft Power Point_.
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* Timing diagrams made with _WaveDrom Editor_.
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* Documentation proudly made with `asciidoctor`.
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* "Segger Embedded Studio" and "J-Link" are trademarks of Segger Microcontroller Systems GmbH.
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* All further/unreferenced products belong to their according copyright holders.
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PDF icons from https://www.flaticon.com and made by
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link:https://www.freepik.com[Freepik], link:https://www.flaticon.com/authors/good-ware[Good Ware],
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link:https://www.flaticon.com/authors/pixel-perfect[Pixel perfect], link:https://www.flaticon.com/authors/vectors-market[Vectors Market]
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=== Disclaimer
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This project is released under the BSD 3-Clause license. No copyright infringement
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intended. Other implied or used projects might have different licensing – see their documentation to get more information.
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:sectnums!:
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=== Limitation of Liability for External Links
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This document contains links to the websites of third parties ("external links"). As the content of these websites
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is not under our control, we cannot assume any liability for such external content. In all cases, the provider of
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information of the linked websites is liable for the content and accuracy of the information provided. At the
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point in time when the links were placed, no infringements of the law were recognizable to us. As soon as an
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infringement of the law becomes known to us, we will immediately remove the link in question.
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:sectnums!:
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=== Citing
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[NOTE]
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This is an open-source project that is free of charge. Use this project in any way you like
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(as long as it complies to the permissive license). Please cite it appropriately. 👍
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.Contributors ❤️
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[NOTE]
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Please add as many https://github.com/stnolting/neorv32/graphs/contributors[contributors] as possible to the `author` field. +
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This project would not be where it is without them.
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If you are using the NEORV32 or parts of the project in some kind of publication, please cite it as follows:
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.BibTeX
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[source]
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----
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@misc{nolting22,
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author = {Nolting, S. and ...},
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title = {The NEORV32 RISC-V Processor},
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year = {2022},
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publisher = {GitHub},
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journal = {GitHub repository},
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howpublished = {\url{https://github.com/stnolting/neorv32}}
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}
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----
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.DOI
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[TIP]
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This project also provides a _digital object identifier_ provided by https://zenodo.org[zenodo]:
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https://doi.org/10.5281/zenodo.5018888[image:https://zenodo.org/badge/DOI/10.5281/zenodo.5018888.svg[title='zenodo']]
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:sectnums!:
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=== Acknowledgments
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**A big shout-out to the community and all https://github.com/stnolting/neorv32/graphs/contributors[contributors],
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who helped improving this project! ❤️**
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https://riscv.org[RISC-V] - instruction sets want to be free!
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Continuous integration provided by https://github.com/features/actions[GitHub Actions] and powered by https://github.com/ghdl/ghdl[GHDL].
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