495 lines
16 KiB
C
495 lines
16 KiB
C
/*
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* QTests for Nuvoton NPCM7xx SMBus Modules.
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*
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* Copyright 2020 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "libqos/i2c.h"
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#include "libqtest.h"
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#include "hw/sensor/tmp105_regs.h"
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#define NR_SMBUS_DEVICES 16
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#define SMBUS_ADDR(x) (0xf0080000 + 0x1000 * (x))
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#define SMBUS_IRQ(x) (64 + (x))
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#define EVB_DEVICE_ADDR 0x48
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#define INVALID_DEVICE_ADDR 0x01
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const int evb_bus_list[] = {0, 1, 2, 6};
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/* Offsets */
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enum CommonRegister {
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OFFSET_SDA = 0x0,
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OFFSET_ST = 0x2,
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OFFSET_CST = 0x4,
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OFFSET_CTL1 = 0x6,
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OFFSET_ADDR1 = 0x8,
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OFFSET_CTL2 = 0xa,
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OFFSET_ADDR2 = 0xc,
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OFFSET_CTL3 = 0xe,
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OFFSET_CST2 = 0x18,
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OFFSET_CST3 = 0x19,
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};
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enum NPCM7xxSMBusBank0Register {
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OFFSET_ADDR3 = 0x10,
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OFFSET_ADDR7 = 0x11,
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OFFSET_ADDR4 = 0x12,
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OFFSET_ADDR8 = 0x13,
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OFFSET_ADDR5 = 0x14,
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OFFSET_ADDR9 = 0x15,
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OFFSET_ADDR6 = 0x16,
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OFFSET_ADDR10 = 0x17,
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OFFSET_CTL4 = 0x1a,
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OFFSET_CTL5 = 0x1b,
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OFFSET_SCLLT = 0x1c,
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OFFSET_FIF_CTL = 0x1d,
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OFFSET_SCLHT = 0x1e,
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};
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enum NPCM7xxSMBusBank1Register {
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OFFSET_FIF_CTS = 0x10,
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OFFSET_FAIR_PER = 0x11,
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OFFSET_TXF_CTL = 0x12,
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OFFSET_T_OUT = 0x14,
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OFFSET_TXF_STS = 0x1a,
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OFFSET_RXF_STS = 0x1c,
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OFFSET_RXF_CTL = 0x1e,
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};
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/* ST fields */
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#define ST_STP BIT(7)
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#define ST_SDAST BIT(6)
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#define ST_BER BIT(5)
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#define ST_NEGACK BIT(4)
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#define ST_STASTR BIT(3)
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#define ST_NMATCH BIT(2)
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#define ST_MODE BIT(1)
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#define ST_XMIT BIT(0)
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/* CST fields */
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#define CST_ARPMATCH BIT(7)
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#define CST_MATCHAF BIT(6)
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#define CST_TGSCL BIT(5)
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#define CST_TSDA BIT(4)
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#define CST_GCMATCH BIT(3)
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#define CST_MATCH BIT(2)
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#define CST_BB BIT(1)
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#define CST_BUSY BIT(0)
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/* CST2 fields */
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#define CST2_INSTTS BIT(7)
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#define CST2_MATCH7F BIT(6)
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#define CST2_MATCH6F BIT(5)
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#define CST2_MATCH5F BIT(4)
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#define CST2_MATCH4F BIT(3)
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#define CST2_MATCH3F BIT(2)
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#define CST2_MATCH2F BIT(1)
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#define CST2_MATCH1F BIT(0)
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/* CST3 fields */
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#define CST3_EO_BUSY BIT(7)
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#define CST3_MATCH10F BIT(2)
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#define CST3_MATCH9F BIT(1)
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#define CST3_MATCH8F BIT(0)
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/* CTL1 fields */
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#define CTL1_STASTRE BIT(7)
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#define CTL1_NMINTE BIT(6)
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#define CTL1_GCMEN BIT(5)
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#define CTL1_ACK BIT(4)
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#define CTL1_EOBINTE BIT(3)
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#define CTL1_INTEN BIT(2)
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#define CTL1_STOP BIT(1)
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#define CTL1_START BIT(0)
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/* CTL2 fields */
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#define CTL2_SCLFRQ(rv) extract8((rv), 1, 6)
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#define CTL2_ENABLE BIT(0)
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/* CTL3 fields */
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#define CTL3_SCL_LVL BIT(7)
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#define CTL3_SDA_LVL BIT(6)
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#define CTL3_BNK_SEL BIT(5)
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#define CTL3_400K_MODE BIT(4)
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#define CTL3_IDL_START BIT(3)
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#define CTL3_ARPMEN BIT(2)
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#define CTL3_SCLFRQ(rv) extract8((rv), 0, 2)
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/* ADDR fields */
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#define ADDR_EN BIT(7)
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#define ADDR_A(rv) extract8((rv), 0, 6)
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/* FIF_CTL fields */
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#define FIF_CTL_FIFO_EN BIT(4)
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/* FIF_CTS fields */
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#define FIF_CTS_CLR_FIFO BIT(6)
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#define FIF_CTS_RFTE_IE BIT(3)
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#define FIF_CTS_RXF_TXE BIT(1)
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/* TXF_CTL fields */
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#define TXF_CTL_THR_TXIE BIT(6)
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#define TXF_CTL_TX_THR(rv) extract8((rv), 0, 5)
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/* TXF_STS fields */
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#define TXF_STS_TX_THST BIT(6)
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#define TXF_STS_TX_BYTES(rv) extract8((rv), 0, 5)
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/* RXF_CTL fields */
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#define RXF_CTL_THR_RXIE BIT(6)
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#define RXF_CTL_LAST BIT(5)
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#define RXF_CTL_RX_THR(rv) extract8((rv), 0, 5)
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/* RXF_STS fields */
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#define RXF_STS_RX_THST BIT(6)
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#define RXF_STS_RX_BYTES(rv) extract8((rv), 0, 5)
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static void choose_bank(QTestState *qts, uint64_t base_addr, uint8_t bank)
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{
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uint8_t ctl3 = qtest_readb(qts, base_addr + OFFSET_CTL3);
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if (bank) {
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ctl3 |= CTL3_BNK_SEL;
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} else {
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ctl3 &= ~CTL3_BNK_SEL;
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}
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qtest_writeb(qts, base_addr + OFFSET_CTL3, ctl3);
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}
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static void check_running(QTestState *qts, uint64_t base_addr)
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{
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g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY);
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g_assert_true(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB);
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}
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static void check_stopped(QTestState *qts, uint64_t base_addr)
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{
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uint8_t cst3;
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0);
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g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BUSY);
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g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST) & CST_BB);
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cst3 = qtest_readb(qts, base_addr + OFFSET_CST3);
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g_assert_true(cst3 & CST3_EO_BUSY);
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qtest_writeb(qts, base_addr + OFFSET_CST3, cst3);
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cst3 = qtest_readb(qts, base_addr + OFFSET_CST3);
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g_assert_false(cst3 & CST3_EO_BUSY);
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}
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static void enable_bus(QTestState *qts, uint64_t base_addr)
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{
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uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2);
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ctl2 |= CTL2_ENABLE;
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qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2);
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g_assert_true(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE);
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}
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static void disable_bus(QTestState *qts, uint64_t base_addr)
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{
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uint8_t ctl2 = qtest_readb(qts, base_addr + OFFSET_CTL2);
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ctl2 &= ~CTL2_ENABLE;
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qtest_writeb(qts, base_addr + OFFSET_CTL2, ctl2);
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g_assert_false(qtest_readb(qts, base_addr + OFFSET_CTL2) & CTL2_ENABLE);
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}
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static void start_transfer(QTestState *qts, uint64_t base_addr)
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{
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uint8_t ctl1;
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ctl1 = CTL1_START | CTL1_INTEN | CTL1_STASTRE;
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qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1);
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==,
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CTL1_INTEN | CTL1_STASTRE | CTL1_INTEN);
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==,
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ST_MODE | ST_XMIT | ST_SDAST);
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check_running(qts, base_addr);
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}
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static void stop_transfer(QTestState *qts, uint64_t base_addr)
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{
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uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1);
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ctl1 &= ~(CTL1_START | CTL1_ACK);
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ctl1 |= CTL1_STOP | CTL1_INTEN | CTL1_EOBINTE;
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qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1);
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ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1);
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g_assert_false(ctl1 & CTL1_STOP);
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}
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static void send_byte(QTestState *qts, uint64_t base_addr, uint8_t byte)
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{
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==,
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ST_MODE | ST_XMIT | ST_SDAST);
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qtest_writeb(qts, base_addr + OFFSET_SDA, byte);
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}
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static bool check_recv(QTestState *qts, uint64_t base_addr)
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{
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uint8_t st, fif_ctl, rxf_ctl, rxf_sts;
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bool fifo;
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st = qtest_readb(qts, base_addr + OFFSET_ST);
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choose_bank(qts, base_addr, 0);
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fif_ctl = qtest_readb(qts, base_addr + OFFSET_FIF_CTL);
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fifo = fif_ctl & FIF_CTL_FIFO_EN;
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if (!fifo) {
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return st == (ST_MODE | ST_SDAST);
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}
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choose_bank(qts, base_addr, 1);
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rxf_ctl = qtest_readb(qts, base_addr + OFFSET_RXF_CTL);
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rxf_sts = qtest_readb(qts, base_addr + OFFSET_RXF_STS);
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if ((rxf_ctl & RXF_CTL_THR_RXIE) && RXF_STS_RX_BYTES(rxf_sts) < 16) {
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return st == ST_MODE;
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} else {
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return st == (ST_MODE | ST_SDAST);
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}
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}
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static uint8_t recv_byte(QTestState *qts, uint64_t base_addr)
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{
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g_assert_true(check_recv(qts, base_addr));
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return qtest_readb(qts, base_addr + OFFSET_SDA);
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}
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static void send_address(QTestState *qts, uint64_t base_addr, uint8_t addr,
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bool recv, bool valid)
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{
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uint8_t encoded_addr = (addr << 1) | (recv ? 1 : 0);
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uint8_t st;
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qtest_writeb(qts, base_addr + OFFSET_SDA, encoded_addr);
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st = qtest_readb(qts, base_addr + OFFSET_ST);
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if (valid) {
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if (recv) {
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g_assert_cmphex(st, ==, ST_MODE | ST_SDAST | ST_STASTR);
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} else {
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g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_SDAST | ST_STASTR);
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}
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qtest_writeb(qts, base_addr + OFFSET_ST, ST_STASTR);
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st = qtest_readb(qts, base_addr + OFFSET_ST);
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if (recv) {
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g_assert_true(check_recv(qts, base_addr));
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} else {
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g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_SDAST);
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}
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} else {
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if (recv) {
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g_assert_cmphex(st, ==, ST_MODE | ST_NEGACK);
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} else {
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g_assert_cmphex(st, ==, ST_MODE | ST_XMIT | ST_NEGACK);
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}
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}
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}
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static void send_nack(QTestState *qts, uint64_t base_addr)
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{
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uint8_t ctl1 = qtest_readb(qts, base_addr + OFFSET_CTL1);
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ctl1 &= ~(CTL1_START | CTL1_STOP);
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ctl1 |= CTL1_ACK | CTL1_INTEN;
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qtest_writeb(qts, base_addr + OFFSET_CTL1, ctl1);
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}
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static void start_fifo_mode(QTestState *qts, uint64_t base_addr)
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{
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choose_bank(qts, base_addr, 0);
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qtest_writeb(qts, base_addr + OFFSET_FIF_CTL, FIF_CTL_FIFO_EN);
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g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTL) &
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FIF_CTL_FIFO_EN);
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choose_bank(qts, base_addr, 1);
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qtest_writeb(qts, base_addr + OFFSET_FIF_CTS,
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FIF_CTS_CLR_FIFO | FIF_CTS_RFTE_IE);
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_FIF_CTS), ==,
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FIF_CTS_RFTE_IE);
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_TXF_STS), ==, 0);
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_RXF_STS), ==, 0);
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}
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static void start_recv_fifo(QTestState *qts, uint64_t base_addr, uint8_t bytes)
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{
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choose_bank(qts, base_addr, 1);
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qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, 0);
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qtest_writeb(qts, base_addr + OFFSET_RXF_CTL,
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RXF_CTL_THR_RXIE | RXF_CTL_LAST | bytes);
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}
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/* Check the SMBus's status is set correctly when disabled. */
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static void test_disable_bus(gconstpointer data)
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{
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intptr_t index = (intptr_t)data;
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uint64_t base_addr = SMBUS_ADDR(index);
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QTestState *qts = qtest_init("-machine npcm750-evb");
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disable_bus(qts, base_addr);
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CTL1), ==, 0);
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_ST), ==, 0);
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g_assert_false(qtest_readb(qts, base_addr + OFFSET_CST3) & CST3_EO_BUSY);
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g_assert_cmphex(qtest_readb(qts, base_addr + OFFSET_CST), ==, 0);
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qtest_quit(qts);
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}
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/* Check the SMBus returns a NACK for an invalid address. */
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static void test_invalid_addr(gconstpointer data)
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{
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intptr_t index = (intptr_t)data;
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uint64_t base_addr = SMBUS_ADDR(index);
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int irq = SMBUS_IRQ(index);
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QTestState *qts = qtest_init("-machine npcm750-evb");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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enable_bus(qts, base_addr);
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g_assert_false(qtest_get_irq(qts, irq));
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start_transfer(qts, base_addr);
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send_address(qts, base_addr, INVALID_DEVICE_ADDR, false, false);
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g_assert_true(qtest_get_irq(qts, irq));
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stop_transfer(qts, base_addr);
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check_running(qts, base_addr);
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qtest_writeb(qts, base_addr + OFFSET_ST, ST_NEGACK);
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g_assert_false(qtest_readb(qts, base_addr + OFFSET_ST) & ST_NEGACK);
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check_stopped(qts, base_addr);
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qtest_quit(qts);
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}
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/* Check the SMBus can send and receive bytes to a device in single mode. */
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static void test_single_mode(gconstpointer data)
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{
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intptr_t index = (intptr_t)data;
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uint64_t base_addr = SMBUS_ADDR(index);
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int irq = SMBUS_IRQ(index);
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uint8_t value = 0x60;
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QTestState *qts = qtest_init("-machine npcm750-evb");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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enable_bus(qts, base_addr);
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/* Sending */
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g_assert_false(qtest_get_irq(qts, irq));
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start_transfer(qts, base_addr);
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g_assert_true(qtest_get_irq(qts, irq));
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send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true);
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send_byte(qts, base_addr, TMP105_REG_CONFIG);
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send_byte(qts, base_addr, value);
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stop_transfer(qts, base_addr);
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check_stopped(qts, base_addr);
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/* Receiving */
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start_transfer(qts, base_addr);
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send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true);
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send_byte(qts, base_addr, TMP105_REG_CONFIG);
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start_transfer(qts, base_addr);
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send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true);
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send_nack(qts, base_addr);
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stop_transfer(qts, base_addr);
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check_running(qts, base_addr);
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g_assert_cmphex(recv_byte(qts, base_addr), ==, value);
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check_stopped(qts, base_addr);
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qtest_quit(qts);
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}
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/* Check the SMBus can send and receive bytes in FIFO mode. */
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static void test_fifo_mode(gconstpointer data)
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{
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intptr_t index = (intptr_t)data;
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uint64_t base_addr = SMBUS_ADDR(index);
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int irq = SMBUS_IRQ(index);
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uint8_t value = 0x60;
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QTestState *qts = qtest_init("-machine npcm750-evb");
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qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
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enable_bus(qts, base_addr);
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start_fifo_mode(qts, base_addr);
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g_assert_false(qtest_get_irq(qts, irq));
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/* Sending */
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start_transfer(qts, base_addr);
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send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true);
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choose_bank(qts, base_addr, 1);
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g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) &
|
|
FIF_CTS_RXF_TXE);
|
|
qtest_writeb(qts, base_addr + OFFSET_TXF_CTL, TXF_CTL_THR_TXIE);
|
|
send_byte(qts, base_addr, TMP105_REG_CONFIG);
|
|
send_byte(qts, base_addr, value);
|
|
g_assert_true(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) &
|
|
FIF_CTS_RXF_TXE);
|
|
g_assert_true(qtest_readb(qts, base_addr + OFFSET_TXF_STS) &
|
|
TXF_STS_TX_THST);
|
|
g_assert_cmpuint(TXF_STS_TX_BYTES(
|
|
qtest_readb(qts, base_addr + OFFSET_TXF_STS)), ==, 0);
|
|
g_assert_true(qtest_get_irq(qts, irq));
|
|
stop_transfer(qts, base_addr);
|
|
check_stopped(qts, base_addr);
|
|
|
|
/* Receiving */
|
|
start_fifo_mode(qts, base_addr);
|
|
start_transfer(qts, base_addr);
|
|
send_address(qts, base_addr, EVB_DEVICE_ADDR, false, true);
|
|
send_byte(qts, base_addr, TMP105_REG_CONFIG);
|
|
start_transfer(qts, base_addr);
|
|
qtest_writeb(qts, base_addr + OFFSET_FIF_CTS, FIF_CTS_RXF_TXE);
|
|
start_recv_fifo(qts, base_addr, 1);
|
|
send_address(qts, base_addr, EVB_DEVICE_ADDR, true, true);
|
|
g_assert_false(qtest_readb(qts, base_addr + OFFSET_FIF_CTS) &
|
|
FIF_CTS_RXF_TXE);
|
|
g_assert_true(qtest_readb(qts, base_addr + OFFSET_RXF_STS) &
|
|
RXF_STS_RX_THST);
|
|
g_assert_cmpuint(RXF_STS_RX_BYTES(
|
|
qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 1);
|
|
send_nack(qts, base_addr);
|
|
stop_transfer(qts, base_addr);
|
|
check_running(qts, base_addr);
|
|
g_assert_cmphex(recv_byte(qts, base_addr), ==, value);
|
|
g_assert_cmpuint(RXF_STS_RX_BYTES(
|
|
qtest_readb(qts, base_addr + OFFSET_RXF_STS)), ==, 0);
|
|
check_stopped(qts, base_addr);
|
|
qtest_quit(qts);
|
|
}
|
|
|
|
static void smbus_add_test(const char *name, int index, GTestDataFunc fn)
|
|
{
|
|
g_autofree char *full_name = g_strdup_printf(
|
|
"npcm7xx_smbus[%d]/%s", index, name);
|
|
qtest_add_data_func(full_name, (void *)(intptr_t)index, fn);
|
|
}
|
|
#define add_test(name, td) smbus_add_test(#name, td, test_##name)
|
|
|
|
int main(int argc, char **argv)
|
|
{
|
|
int i;
|
|
|
|
g_test_init(&argc, &argv, NULL);
|
|
g_test_set_nonfatal_assertions();
|
|
|
|
for (i = 0; i < NR_SMBUS_DEVICES; ++i) {
|
|
add_test(disable_bus, i);
|
|
add_test(invalid_addr, i);
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(evb_bus_list); ++i) {
|
|
add_test(single_mode, evb_bus_list[i]);
|
|
add_test(fifo_mode, evb_bus_list[i]);
|
|
}
|
|
|
|
return g_test_run();
|
|
}
|