228 lines
7.3 KiB
C
228 lines
7.3 KiB
C
/*
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* QEMU model of the VersalUsb2CtrlRegs Register control/Status block for
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* USB2.0 controller
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*
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* This module should control phy_reset, permanent device plugs, frame length
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* time adjust & setting of coherency paths. None of which are emulated in
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* present model.
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*
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* Copyright (c) 2020 Xilinx Inc. Vikram Garhwal <fnu.vikram@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/irq.h"
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#include "hw/register.h"
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#include "qemu/bitops.h"
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#include "qom/object.h"
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#include "migration/vmstate.h"
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#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h"
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#ifndef XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG
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#define XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG 0
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#endif
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REG32(BUS_FILTER, 0x30)
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FIELD(BUS_FILTER, BYPASS, 0, 4)
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REG32(PORT, 0x34)
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FIELD(PORT, HOST_SMI_BAR_WR, 4, 1)
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FIELD(PORT, HOST_SMI_PCI_CMD_REG_WR, 3, 1)
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FIELD(PORT, HOST_MSI_ENABLE, 2, 1)
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FIELD(PORT, PWR_CTRL_PRSNT, 1, 1)
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FIELD(PORT, HUB_PERM_ATTACH, 0, 1)
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REG32(JITTER_ADJUST, 0x38)
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FIELD(JITTER_ADJUST, FLADJ, 0, 6)
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REG32(BIGENDIAN, 0x40)
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FIELD(BIGENDIAN, ENDIAN_GS, 0, 1)
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REG32(COHERENCY, 0x44)
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FIELD(COHERENCY, USB_COHERENCY, 0, 1)
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REG32(XHC_BME, 0x48)
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FIELD(XHC_BME, XHC_BME, 0, 1)
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REG32(REG_CTRL, 0x60)
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FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1)
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REG32(IR_STATUS, 0x64)
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FIELD(IR_STATUS, HOST_SYS_ERR, 1, 1)
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FIELD(IR_STATUS, ADDR_DEC_ERR, 0, 1)
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REG32(IR_MASK, 0x68)
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FIELD(IR_MASK, HOST_SYS_ERR, 1, 1)
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FIELD(IR_MASK, ADDR_DEC_ERR, 0, 1)
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REG32(IR_ENABLE, 0x6c)
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FIELD(IR_ENABLE, HOST_SYS_ERR, 1, 1)
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FIELD(IR_ENABLE, ADDR_DEC_ERR, 0, 1)
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REG32(IR_DISABLE, 0x70)
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FIELD(IR_DISABLE, HOST_SYS_ERR, 1, 1)
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FIELD(IR_DISABLE, ADDR_DEC_ERR, 0, 1)
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REG32(USB3, 0x78)
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static void ir_update_irq(VersalUsb2CtrlRegs *s)
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{
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bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
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qemu_set_irq(s->irq_ir, pending);
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}
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static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
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{
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VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
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/*
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* TODO: This should also clear USBSTS.HSE field in USB XHCI register.
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* May be combine both the modules.
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*/
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ir_update_irq(s);
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}
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static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
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{
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VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IR_MASK] &= ~val;
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ir_update_irq(s);
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return 0;
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}
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static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
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{
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VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IR_MASK] |= val;
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ir_update_irq(s);
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return 0;
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}
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static const RegisterAccessInfo usb2_ctrl_regs_regs_info[] = {
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{ .name = "BUS_FILTER", .addr = A_BUS_FILTER,
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.rsvd = 0xfffffff0,
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},{ .name = "PORT", .addr = A_PORT,
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.rsvd = 0xffffffe0,
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},{ .name = "JITTER_ADJUST", .addr = A_JITTER_ADJUST,
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.reset = 0x20,
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.rsvd = 0xffffffc0,
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},{ .name = "BIGENDIAN", .addr = A_BIGENDIAN,
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.rsvd = 0xfffffffe,
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},{ .name = "COHERENCY", .addr = A_COHERENCY,
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.rsvd = 0xfffffffe,
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},{ .name = "XHC_BME", .addr = A_XHC_BME,
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.reset = 0x1,
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.rsvd = 0xfffffffe,
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},{ .name = "REG_CTRL", .addr = A_REG_CTRL,
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.rsvd = 0xfffffffe,
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},{ .name = "IR_STATUS", .addr = A_IR_STATUS,
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.rsvd = 0xfffffffc,
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.w1c = 0x3,
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.post_write = ir_status_postw,
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},{ .name = "IR_MASK", .addr = A_IR_MASK,
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.reset = 0x3,
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.rsvd = 0xfffffffc,
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.ro = 0x3,
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},{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
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.rsvd = 0xfffffffc,
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.pre_write = ir_enable_prew,
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},{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
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.rsvd = 0xfffffffc,
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.pre_write = ir_disable_prew,
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},{ .name = "USB3", .addr = A_USB3,
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}
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};
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static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type)
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{
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VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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register_reset(&s->regs_info[i]);
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}
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}
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static void usb2_ctrl_regs_reset_hold(Object *obj)
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{
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VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
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ir_update_irq(s);
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}
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static const MemoryRegionOps usb2_ctrl_regs_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void usb2_ctrl_regs_init(Object *obj)
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{
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VersalUsb2CtrlRegs *s = XILINX_VERSAL_USB2_CTRL_REGS(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
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USB2_REGS_R_MAX * 4);
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reg_array =
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register_init_block32(DEVICE(obj), usb2_ctrl_regs_regs_info,
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ARRAY_SIZE(usb2_ctrl_regs_regs_info),
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s->regs_info, s->regs,
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&usb2_ctrl_regs_ops,
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XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG,
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USB2_REGS_R_MAX * 4);
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memory_region_add_subregion(&s->iomem,
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0x0,
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®_array->mem);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq_ir);
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}
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static const VMStateDescription vmstate_usb2_ctrl_regs = {
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.name = TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, VersalUsb2CtrlRegs, USB2_REGS_R_MAX),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void usb2_ctrl_regs_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.enter = usb2_ctrl_regs_reset_init;
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rc->phases.hold = usb2_ctrl_regs_reset_hold;
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dc->vmsd = &vmstate_usb2_ctrl_regs;
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}
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static const TypeInfo usb2_ctrl_regs_info = {
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.name = TYPE_XILINX_VERSAL_USB2_CTRL_REGS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(VersalUsb2CtrlRegs),
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.class_init = usb2_ctrl_regs_class_init,
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.instance_init = usb2_ctrl_regs_init,
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};
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static void usb2_ctrl_regs_register_types(void)
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{
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type_register_static(&usb2_ctrl_regs_info);
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}
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type_init(usb2_ctrl_regs_register_types)
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