377 lines
10 KiB
C
377 lines
10 KiB
C
/*
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* IMX EPIT Timer
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*
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* Copyright (c) 2008 OK Labs
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* Copyright (c) 2011 NICTA Pty Ltd
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* Originally written by Hans Jiang
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* Updated by Peter Chubb
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This code is licensed under GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/timer/imx_epit.h"
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#include "migration/vmstate.h"
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#include "hw/irq.h"
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#include "hw/misc/imx_ccm.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#ifndef DEBUG_IMX_EPIT
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#define DEBUG_IMX_EPIT 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_EPIT) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \
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__func__, ##args); \
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} \
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} while (0)
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static const char *imx_epit_reg_name(uint32_t reg)
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{
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switch (reg) {
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case 0:
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return "CR";
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case 1:
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return "SR";
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case 2:
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return "LR";
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case 3:
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return "CMP";
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case 4:
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return "CNT";
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default:
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return "[?]";
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}
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}
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/*
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* Exact clock frequencies vary from board to board.
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* These are typical.
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*/
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static const IMXClk imx_epit_clocks[] = {
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CLK_NONE, /* 00 disabled */
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CLK_IPG, /* 01 ipg_clk, ~532MHz */
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CLK_IPG_HIGH, /* 10 ipg_clk_highfreq */
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CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */
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};
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/*
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* Update interrupt status
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*/
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static void imx_epit_update_int(IMXEPITState *s)
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{
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if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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/*
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* Must be called from within a ptimer_transaction_begin/commit block
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* for both s->timer_cmp and s->timer_reload.
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*/
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static void imx_epit_set_freq(IMXEPITState *s)
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{
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uint32_t clksrc;
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uint32_t prescaler;
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clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2);
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prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12);
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s->freq = imx_ccm_get_clock_frequency(s->ccm,
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imx_epit_clocks[clksrc]) / prescaler;
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DPRINTF("Setting ptimer frequency to %u\n", s->freq);
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if (s->freq) {
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ptimer_set_freq(s->timer_reload, s->freq);
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ptimer_set_freq(s->timer_cmp, s->freq);
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}
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}
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static void imx_epit_reset(DeviceState *dev)
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{
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IMXEPITState *s = IMX_EPIT(dev);
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/*
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* Soft reset doesn't touch some bits; hard reset clears them
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*/
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s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN);
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s->sr = 0;
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s->lr = EPIT_TIMER_MAX;
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s->cmp = 0;
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s->cnt = 0;
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ptimer_transaction_begin(s->timer_cmp);
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ptimer_transaction_begin(s->timer_reload);
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/* stop both timers */
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ptimer_stop(s->timer_cmp);
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ptimer_stop(s->timer_reload);
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/* compute new frequency */
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imx_epit_set_freq(s);
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/* init both timers to EPIT_TIMER_MAX */
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ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
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ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
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if (s->freq && (s->cr & CR_EN)) {
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/* if the timer is still enabled, restart it */
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ptimer_run(s->timer_reload, 0);
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}
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ptimer_transaction_commit(s->timer_cmp);
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ptimer_transaction_commit(s->timer_reload);
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}
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static uint32_t imx_epit_update_count(IMXEPITState *s)
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{
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s->cnt = ptimer_get_count(s->timer_reload);
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return s->cnt;
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}
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static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size)
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{
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IMXEPITState *s = IMX_EPIT(opaque);
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uint32_t reg_value = 0;
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switch (offset >> 2) {
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case 0: /* Control Register */
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reg_value = s->cr;
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break;
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case 1: /* Status Register */
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reg_value = s->sr;
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break;
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case 2: /* LR - ticks*/
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reg_value = s->lr;
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break;
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case 3: /* CMP */
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reg_value = s->cmp;
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break;
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case 4: /* CNT */
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imx_epit_update_count(s);
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reg_value = s->cnt;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
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break;
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}
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DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value);
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return reg_value;
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}
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/* Must be called from ptimer_transaction_begin/commit block for s->timer_cmp */
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static void imx_epit_reload_compare_timer(IMXEPITState *s)
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{
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if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) {
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/* if the compare feature is on and timers are running */
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uint32_t tmp = imx_epit_update_count(s);
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uint64_t next;
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if (tmp > s->cmp) {
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/* It'll fire in this round of the timer */
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next = tmp - s->cmp;
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} else { /* catch it next time around */
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next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr);
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}
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ptimer_set_count(s->timer_cmp, next);
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}
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}
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static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMXEPITState *s = IMX_EPIT(opaque);
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uint64_t oldcr;
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DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2),
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(uint32_t)value);
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switch (offset >> 2) {
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case 0: /* CR */
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oldcr = s->cr;
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s->cr = value & 0x03ffffff;
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if (s->cr & CR_SWR) {
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/* handle the reset */
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imx_epit_reset(DEVICE(s));
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/*
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* TODO: could we 'break' here? following operations appear
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* to duplicate the work imx_epit_reset() already did.
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*/
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}
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ptimer_transaction_begin(s->timer_cmp);
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ptimer_transaction_begin(s->timer_reload);
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if (!(s->cr & CR_SWR)) {
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imx_epit_set_freq(s);
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}
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if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) {
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if (s->cr & CR_ENMOD) {
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if (s->cr & CR_RLD) {
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ptimer_set_limit(s->timer_reload, s->lr, 1);
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ptimer_set_limit(s->timer_cmp, s->lr, 1);
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} else {
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ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1);
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ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1);
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}
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}
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imx_epit_reload_compare_timer(s);
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ptimer_run(s->timer_reload, 0);
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if (s->cr & CR_OCIEN) {
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ptimer_run(s->timer_cmp, 0);
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} else {
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ptimer_stop(s->timer_cmp);
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}
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} else if (!(s->cr & CR_EN)) {
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/* stop both timers */
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ptimer_stop(s->timer_reload);
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ptimer_stop(s->timer_cmp);
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} else if (s->cr & CR_OCIEN) {
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if (!(oldcr & CR_OCIEN)) {
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imx_epit_reload_compare_timer(s);
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ptimer_run(s->timer_cmp, 0);
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}
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} else {
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ptimer_stop(s->timer_cmp);
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}
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ptimer_transaction_commit(s->timer_cmp);
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ptimer_transaction_commit(s->timer_reload);
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break;
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case 1: /* SR - ACK*/
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/* writing 1 to OCIF clear the OCIF bit */
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if (value & 0x01) {
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s->sr = 0;
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imx_epit_update_int(s);
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}
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break;
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case 2: /* LR - set ticks */
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s->lr = value;
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ptimer_transaction_begin(s->timer_cmp);
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ptimer_transaction_begin(s->timer_reload);
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if (s->cr & CR_RLD) {
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/* Also set the limit if the LRD bit is set */
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/* If IOVW bit is set then set the timer value */
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ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW);
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ptimer_set_limit(s->timer_cmp, s->lr, 0);
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} else if (s->cr & CR_IOVW) {
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/* If IOVW bit is set then set the timer value */
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ptimer_set_count(s->timer_reload, s->lr);
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}
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imx_epit_reload_compare_timer(s);
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ptimer_transaction_commit(s->timer_cmp);
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ptimer_transaction_commit(s->timer_reload);
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break;
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case 3: /* CMP */
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s->cmp = value;
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ptimer_transaction_begin(s->timer_cmp);
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imx_epit_reload_compare_timer(s);
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ptimer_transaction_commit(s->timer_cmp);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset);
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break;
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}
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}
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static void imx_epit_cmp(void *opaque)
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{
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IMXEPITState *s = IMX_EPIT(opaque);
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DPRINTF("sr was %d\n", s->sr);
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s->sr = 1;
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imx_epit_update_int(s);
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}
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static void imx_epit_reload(void *opaque)
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{
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/* No action required on rollover of timer_reload */
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}
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static const MemoryRegionOps imx_epit_ops = {
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.read = imx_epit_read,
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.write = imx_epit_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_imx_timer_epit = {
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.name = TYPE_IMX_EPIT,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(cr, IMXEPITState),
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VMSTATE_UINT32(sr, IMXEPITState),
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VMSTATE_UINT32(lr, IMXEPITState),
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VMSTATE_UINT32(cmp, IMXEPITState),
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VMSTATE_UINT32(cnt, IMXEPITState),
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VMSTATE_UINT32(freq, IMXEPITState),
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VMSTATE_PTIMER(timer_reload, IMXEPITState),
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VMSTATE_PTIMER(timer_cmp, IMXEPITState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void imx_epit_realize(DeviceState *dev, Error **errp)
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{
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IMXEPITState *s = IMX_EPIT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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DPRINTF("\n");
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT,
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0x00001000);
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sysbus_init_mmio(sbd, &s->iomem);
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s->timer_reload = ptimer_init(imx_epit_reload, s, PTIMER_POLICY_LEGACY);
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s->timer_cmp = ptimer_init(imx_epit_cmp, s, PTIMER_POLICY_LEGACY);
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}
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static void imx_epit_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = imx_epit_realize;
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dc->reset = imx_epit_reset;
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dc->vmsd = &vmstate_imx_timer_epit;
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dc->desc = "i.MX periodic timer";
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}
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static const TypeInfo imx_epit_info = {
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.name = TYPE_IMX_EPIT,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXEPITState),
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.class_init = imx_epit_class_init,
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};
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static void imx_epit_register_types(void)
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{
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type_register_static(&imx_epit_info);
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}
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type_init(imx_epit_register_types)
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