636 lines
19 KiB
C
636 lines
19 KiB
C
/*
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* ARM AHB5 TrustZone Memory Protection Controller emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "hw/registerfields.h"
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#include "hw/irq.h"
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#include "hw/misc/tz-mpc.h"
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#include "hw/qdev-properties.h"
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/* Our IOMMU has two IOMMU indexes, one for secure transactions and one for
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* non-secure transactions.
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*/
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enum {
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IOMMU_IDX_S,
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IOMMU_IDX_NS,
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IOMMU_NUM_INDEXES,
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};
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/* Config registers */
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REG32(CTRL, 0x00)
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FIELD(CTRL, SEC_RESP, 4, 1)
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FIELD(CTRL, AUTOINC, 8, 1)
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FIELD(CTRL, LOCKDOWN, 31, 1)
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REG32(BLK_MAX, 0x10)
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REG32(BLK_CFG, 0x14)
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REG32(BLK_IDX, 0x18)
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REG32(BLK_LUT, 0x1c)
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REG32(INT_STAT, 0x20)
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FIELD(INT_STAT, IRQ, 0, 1)
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REG32(INT_CLEAR, 0x24)
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FIELD(INT_CLEAR, IRQ, 0, 1)
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REG32(INT_EN, 0x28)
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FIELD(INT_EN, IRQ, 0, 1)
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REG32(INT_INFO1, 0x2c)
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REG32(INT_INFO2, 0x30)
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FIELD(INT_INFO2, HMASTER, 0, 16)
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FIELD(INT_INFO2, HNONSEC, 16, 1)
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FIELD(INT_INFO2, CFG_NS, 17, 1)
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REG32(INT_SET, 0x34)
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FIELD(INT_SET, IRQ, 0, 1)
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REG32(PIDR4, 0xfd0)
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REG32(PIDR5, 0xfd4)
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REG32(PIDR6, 0xfd8)
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REG32(PIDR7, 0xfdc)
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REG32(PIDR0, 0xfe0)
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REG32(PIDR1, 0xfe4)
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REG32(PIDR2, 0xfe8)
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REG32(PIDR3, 0xfec)
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REG32(CIDR0, 0xff0)
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REG32(CIDR1, 0xff4)
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REG32(CIDR2, 0xff8)
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REG32(CIDR3, 0xffc)
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static const uint8_t tz_mpc_idregs[] = {
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0x04, 0x00, 0x00, 0x00,
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0x60, 0xb8, 0x1b, 0x00,
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0x0d, 0xf0, 0x05, 0xb1,
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};
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static void tz_mpc_irq_update(TZMPC *s)
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{
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qemu_set_irq(s->irq, s->int_stat && s->int_en);
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}
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static void tz_mpc_iommu_notify(TZMPC *s, uint32_t lutidx,
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uint32_t oldlut, uint32_t newlut)
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{
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/* Called when the LUT word at lutidx has changed from oldlut to newlut;
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* must call the IOMMU notifiers for the changed blocks.
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*/
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IOMMUTLBEvent event = {
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.entry = {
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.addr_mask = s->blocksize - 1,
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}
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};
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hwaddr addr = lutidx * s->blocksize * 32;
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int i;
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for (i = 0; i < 32; i++, addr += s->blocksize) {
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bool block_is_ns;
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if (!((oldlut ^ newlut) & (1 << i))) {
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continue;
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}
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/* This changes the mappings for both the S and the NS space,
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* so we need to do four notifies: an UNMAP then a MAP for each.
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*/
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block_is_ns = newlut & (1 << i);
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trace_tz_mpc_iommu_notify(addr);
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event.entry.iova = addr;
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event.entry.translated_addr = addr;
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event.type = IOMMU_NOTIFIER_UNMAP;
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event.entry.perm = IOMMU_NONE;
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memory_region_notify_iommu(&s->upstream, IOMMU_IDX_S, event);
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memory_region_notify_iommu(&s->upstream, IOMMU_IDX_NS, event);
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event.type = IOMMU_NOTIFIER_MAP;
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event.entry.perm = IOMMU_RW;
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if (block_is_ns) {
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event.entry.target_as = &s->blocked_io_as;
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} else {
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event.entry.target_as = &s->downstream_as;
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}
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memory_region_notify_iommu(&s->upstream, IOMMU_IDX_S, event);
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if (block_is_ns) {
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event.entry.target_as = &s->downstream_as;
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} else {
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event.entry.target_as = &s->blocked_io_as;
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}
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memory_region_notify_iommu(&s->upstream, IOMMU_IDX_NS, event);
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}
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}
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static void tz_mpc_autoinc_idx(TZMPC *s, unsigned access_size)
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{
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/* Auto-increment BLK_IDX if necessary */
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if (access_size == 4 && (s->ctrl & R_CTRL_AUTOINC_MASK)) {
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s->blk_idx++;
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s->blk_idx %= s->blk_max;
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}
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}
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static MemTxResult tz_mpc_reg_read(void *opaque, hwaddr addr,
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uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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TZMPC *s = TZ_MPC(opaque);
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uint64_t r;
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uint32_t offset = addr & ~0x3;
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if (!attrs.secure && offset < A_PIDR4) {
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/* NS accesses can only see the ID registers */
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qemu_log_mask(LOG_GUEST_ERROR,
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"TZ MPC register read: NS access to offset 0x%x\n",
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offset);
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r = 0;
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goto read_out;
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}
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switch (offset) {
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case A_CTRL:
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r = s->ctrl;
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break;
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case A_BLK_MAX:
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r = s->blk_max - 1;
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break;
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case A_BLK_CFG:
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/* We are never in "init in progress state", so this just indicates
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* the block size. s->blocksize == (1 << BLK_CFG + 5), so
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* BLK_CFG == ctz32(s->blocksize) - 5
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*/
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r = ctz32(s->blocksize) - 5;
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break;
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case A_BLK_IDX:
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r = s->blk_idx;
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break;
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case A_BLK_LUT:
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r = s->blk_lut[s->blk_idx];
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tz_mpc_autoinc_idx(s, size);
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break;
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case A_INT_STAT:
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r = s->int_stat;
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break;
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case A_INT_EN:
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r = s->int_en;
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break;
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case A_INT_INFO1:
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r = s->int_info1;
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break;
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case A_INT_INFO2:
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r = s->int_info2;
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break;
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case A_PIDR4:
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case A_PIDR5:
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case A_PIDR6:
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case A_PIDR7:
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case A_PIDR0:
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case A_PIDR1:
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case A_PIDR2:
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case A_PIDR3:
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case A_CIDR0:
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case A_CIDR1:
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case A_CIDR2:
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case A_CIDR3:
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r = tz_mpc_idregs[(offset - A_PIDR4) / 4];
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break;
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case A_INT_CLEAR:
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case A_INT_SET:
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qemu_log_mask(LOG_GUEST_ERROR,
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"TZ MPC register read: write-only offset 0x%x\n",
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offset);
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r = 0;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"TZ MPC register read: bad offset 0x%x\n", offset);
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r = 0;
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break;
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}
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if (size != 4) {
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/* None of our registers are read-sensitive (except BLK_LUT,
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* which can special case the "size not 4" case), so just
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* pull the right bytes out of the word read result.
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*/
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r = extract32(r, (addr & 3) * 8, size * 8);
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}
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read_out:
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trace_tz_mpc_reg_read(addr, r, size);
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*pdata = r;
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return MEMTX_OK;
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}
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static MemTxResult tz_mpc_reg_write(void *opaque, hwaddr addr,
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uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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TZMPC *s = TZ_MPC(opaque);
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uint32_t offset = addr & ~0x3;
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trace_tz_mpc_reg_write(addr, value, size);
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if (!attrs.secure && offset < A_PIDR4) {
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/* NS accesses can only see the ID registers */
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qemu_log_mask(LOG_GUEST_ERROR,
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"TZ MPC register write: NS access to offset 0x%x\n",
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offset);
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return MEMTX_OK;
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}
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if (size != 4) {
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/* Expand the byte or halfword write to a full word size.
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* In most cases we can do this with zeroes; the exceptions
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* are CTRL, BLK_IDX and BLK_LUT.
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*/
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uint32_t oldval;
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switch (offset) {
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case A_CTRL:
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oldval = s->ctrl;
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break;
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case A_BLK_IDX:
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oldval = s->blk_idx;
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break;
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case A_BLK_LUT:
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oldval = s->blk_lut[s->blk_idx];
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break;
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default:
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oldval = 0;
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break;
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}
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value = deposit32(oldval, (addr & 3) * 8, size * 8, value);
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}
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if ((s->ctrl & R_CTRL_LOCKDOWN_MASK) &&
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(offset == A_CTRL || offset == A_BLK_LUT || offset == A_INT_EN)) {
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/* Lockdown mode makes these three registers read-only, and
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* the only way out of it is to reset the device.
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*/
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qemu_log_mask(LOG_GUEST_ERROR, "TZ MPC register write to offset 0x%x "
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"while MPC is in lockdown mode\n", offset);
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return MEMTX_OK;
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}
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switch (offset) {
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case A_CTRL:
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/* We don't implement the 'data gating' feature so all other bits
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* are reserved and we make them RAZ/WI.
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*/
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s->ctrl = value & (R_CTRL_SEC_RESP_MASK |
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R_CTRL_AUTOINC_MASK |
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R_CTRL_LOCKDOWN_MASK);
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break;
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case A_BLK_IDX:
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s->blk_idx = value % s->blk_max;
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break;
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case A_BLK_LUT:
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tz_mpc_iommu_notify(s, s->blk_idx, s->blk_lut[s->blk_idx], value);
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s->blk_lut[s->blk_idx] = value;
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tz_mpc_autoinc_idx(s, size);
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break;
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case A_INT_CLEAR:
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if (value & R_INT_CLEAR_IRQ_MASK) {
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s->int_stat = 0;
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tz_mpc_irq_update(s);
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}
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break;
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case A_INT_EN:
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s->int_en = value & R_INT_EN_IRQ_MASK;
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tz_mpc_irq_update(s);
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break;
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case A_INT_SET:
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if (value & R_INT_SET_IRQ_MASK) {
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s->int_stat = R_INT_STAT_IRQ_MASK;
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tz_mpc_irq_update(s);
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}
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break;
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case A_PIDR4:
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case A_PIDR5:
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case A_PIDR6:
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case A_PIDR7:
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case A_PIDR0:
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case A_PIDR1:
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case A_PIDR2:
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case A_PIDR3:
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case A_CIDR0:
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case A_CIDR1:
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case A_CIDR2:
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case A_CIDR3:
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qemu_log_mask(LOG_GUEST_ERROR,
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"TZ MPC register write: read-only offset 0x%x\n", offset);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"TZ MPC register write: bad offset 0x%x\n", offset);
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break;
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps tz_mpc_reg_ops = {
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.read_with_attrs = tz_mpc_reg_read,
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.write_with_attrs = tz_mpc_reg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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};
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static inline bool tz_mpc_cfg_ns(TZMPC *s, hwaddr addr)
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{
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/* Return the cfg_ns bit from the LUT for the specified address */
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hwaddr blknum = addr / s->blocksize;
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hwaddr blkword = blknum / 32;
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uint32_t blkbit = 1U << (blknum % 32);
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/* This would imply the address was larger than the size we
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* defined this memory region to be, so it can't happen.
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*/
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assert(blkword < s->blk_max);
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return s->blk_lut[blkword] & blkbit;
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}
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static MemTxResult tz_mpc_handle_block(TZMPC *s, hwaddr addr, MemTxAttrs attrs)
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{
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/* Handle a blocked transaction: raise IRQ, capture info, etc */
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if (!s->int_stat) {
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/* First blocked transfer: capture information into INT_INFO1 and
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* INT_INFO2. Subsequent transfers are still blocked but don't
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* capture information until the guest clears the interrupt.
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*/
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s->int_info1 = addr;
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s->int_info2 = 0;
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s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, HMASTER,
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attrs.requester_id & 0xffff);
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s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, HNONSEC,
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~attrs.secure);
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s->int_info2 = FIELD_DP32(s->int_info2, INT_INFO2, CFG_NS,
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tz_mpc_cfg_ns(s, addr));
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s->int_stat |= R_INT_STAT_IRQ_MASK;
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tz_mpc_irq_update(s);
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}
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/* Generate bus error if desired; otherwise RAZ/WI */
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return (s->ctrl & R_CTRL_SEC_RESP_MASK) ? MEMTX_ERROR : MEMTX_OK;
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}
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/* Accesses only reach these read and write functions if the MPC is
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* blocking them; non-blocked accesses go directly to the downstream
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* memory region without passing through this code.
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*/
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static MemTxResult tz_mpc_mem_blocked_read(void *opaque, hwaddr addr,
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uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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TZMPC *s = TZ_MPC(opaque);
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trace_tz_mpc_mem_blocked_read(addr, size, attrs.secure);
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*pdata = 0;
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return tz_mpc_handle_block(s, addr, attrs);
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}
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static MemTxResult tz_mpc_mem_blocked_write(void *opaque, hwaddr addr,
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uint64_t value,
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unsigned size, MemTxAttrs attrs)
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{
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TZMPC *s = TZ_MPC(opaque);
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trace_tz_mpc_mem_blocked_write(addr, value, size, attrs.secure);
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return tz_mpc_handle_block(s, addr, attrs);
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}
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static const MemoryRegionOps tz_mpc_mem_blocked_ops = {
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.read_with_attrs = tz_mpc_mem_blocked_read,
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.write_with_attrs = tz_mpc_mem_blocked_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.impl.min_access_size = 1,
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.impl.max_access_size = 8,
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};
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static IOMMUTLBEntry tz_mpc_translate(IOMMUMemoryRegion *iommu,
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hwaddr addr, IOMMUAccessFlags flags,
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int iommu_idx)
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{
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TZMPC *s = TZ_MPC(container_of(iommu, TZMPC, upstream));
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bool ok;
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IOMMUTLBEntry ret = {
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.iova = addr & ~(s->blocksize - 1),
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.translated_addr = addr & ~(s->blocksize - 1),
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.addr_mask = s->blocksize - 1,
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.perm = IOMMU_RW,
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};
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/* Look at the per-block configuration for this address, and
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* return a TLB entry directing the transaction at either
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* downstream_as or blocked_io_as, as appropriate.
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* If the LUT cfg_ns bit is 1, only non-secure transactions
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* may pass. If the bit is 0, only secure transactions may pass.
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*/
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ok = tz_mpc_cfg_ns(s, addr) == (iommu_idx == IOMMU_IDX_NS);
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trace_tz_mpc_translate(addr, flags,
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iommu_idx == IOMMU_IDX_S ? "S" : "NS",
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ok ? "pass" : "block");
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ret.target_as = ok ? &s->downstream_as : &s->blocked_io_as;
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return ret;
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}
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static int tz_mpc_attrs_to_index(IOMMUMemoryRegion *iommu, MemTxAttrs attrs)
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{
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/* We treat unspecified attributes like secure. Transactions with
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* unspecified attributes come from places like
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* rom_reset() for initial image load, and we want
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* those to pass through the from-reset "everything is secure" config.
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* All the real during-emulation transactions from the CPU will
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* specify attributes.
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*/
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return (attrs.unspecified || attrs.secure) ? IOMMU_IDX_S : IOMMU_IDX_NS;
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}
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static int tz_mpc_num_indexes(IOMMUMemoryRegion *iommu)
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{
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return IOMMU_NUM_INDEXES;
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}
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static void tz_mpc_reset(DeviceState *dev)
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{
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TZMPC *s = TZ_MPC(dev);
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s->ctrl = 0x00000100;
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s->blk_idx = 0;
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s->int_stat = 0;
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s->int_en = 1;
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s->int_info1 = 0;
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s->int_info2 = 0;
|
|
|
|
memset(s->blk_lut, 0, s->blk_max * sizeof(uint32_t));
|
|
}
|
|
|
|
static void tz_mpc_init(Object *obj)
|
|
{
|
|
DeviceState *dev = DEVICE(obj);
|
|
TZMPC *s = TZ_MPC(obj);
|
|
|
|
qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
|
|
}
|
|
|
|
static void tz_mpc_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
Object *obj = OBJECT(dev);
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
|
|
TZMPC *s = TZ_MPC(dev);
|
|
uint64_t size;
|
|
|
|
/* We can't create the upstream end of the port until realize,
|
|
* as we don't know the size of the MR used as the downstream until then.
|
|
* We insist on having a downstream, to avoid complicating the code
|
|
* with handling the "don't know how big this is" case. It's easy
|
|
* enough for the user to create an unimplemented_device as downstream
|
|
* if they have nothing else to plug into this.
|
|
*/
|
|
if (!s->downstream) {
|
|
error_setg(errp, "MPC 'downstream' link not set");
|
|
return;
|
|
}
|
|
|
|
size = memory_region_size(s->downstream);
|
|
|
|
memory_region_init_iommu(&s->upstream, sizeof(s->upstream),
|
|
TYPE_TZ_MPC_IOMMU_MEMORY_REGION,
|
|
obj, "tz-mpc-upstream", size);
|
|
|
|
/* In real hardware the block size is configurable. In QEMU we could
|
|
* make it configurable but will need it to be at least as big as the
|
|
* target page size so we can execute out of the resulting MRs. Guest
|
|
* software is supposed to check the block size using the BLK_CFG
|
|
* register, so make it fixed at the page size.
|
|
*/
|
|
s->blocksize = memory_region_iommu_get_min_page_size(&s->upstream);
|
|
if (size % s->blocksize != 0) {
|
|
error_setg(errp,
|
|
"MPC 'downstream' size %" PRId64
|
|
" is not a multiple of %" HWADDR_PRIx " bytes",
|
|
size, s->blocksize);
|
|
object_unref(OBJECT(&s->upstream));
|
|
return;
|
|
}
|
|
|
|
/* BLK_MAX is the max value of BLK_IDX, which indexes an array of 32-bit
|
|
* words, each bit of which indicates one block.
|
|
*/
|
|
s->blk_max = DIV_ROUND_UP(size / s->blocksize, 32);
|
|
|
|
memory_region_init_io(&s->regmr, obj, &tz_mpc_reg_ops,
|
|
s, "tz-mpc-regs", 0x1000);
|
|
sysbus_init_mmio(sbd, &s->regmr);
|
|
|
|
sysbus_init_mmio(sbd, MEMORY_REGION(&s->upstream));
|
|
|
|
/* This memory region is not exposed to users of this device as a
|
|
* sysbus MMIO region, but is instead used internally as something
|
|
* that our IOMMU translate function might direct accesses to.
|
|
*/
|
|
memory_region_init_io(&s->blocked_io, obj, &tz_mpc_mem_blocked_ops,
|
|
s, "tz-mpc-blocked-io", size);
|
|
|
|
address_space_init(&s->downstream_as, s->downstream,
|
|
"tz-mpc-downstream");
|
|
address_space_init(&s->blocked_io_as, &s->blocked_io,
|
|
"tz-mpc-blocked-io");
|
|
|
|
s->blk_lut = g_new0(uint32_t, s->blk_max);
|
|
}
|
|
|
|
static int tz_mpc_post_load(void *opaque, int version_id)
|
|
{
|
|
TZMPC *s = TZ_MPC(opaque);
|
|
|
|
/* Check the incoming data doesn't point blk_idx off the end of blk_lut. */
|
|
if (s->blk_idx >= s->blk_max) {
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription tz_mpc_vmstate = {
|
|
.name = "tz-mpc",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.post_load = tz_mpc_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(ctrl, TZMPC),
|
|
VMSTATE_UINT32(blk_idx, TZMPC),
|
|
VMSTATE_UINT32(int_stat, TZMPC),
|
|
VMSTATE_UINT32(int_en, TZMPC),
|
|
VMSTATE_UINT32(int_info1, TZMPC),
|
|
VMSTATE_UINT32(int_info2, TZMPC),
|
|
VMSTATE_VARRAY_UINT32(blk_lut, TZMPC, blk_max,
|
|
0, vmstate_info_uint32, uint32_t),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static Property tz_mpc_properties[] = {
|
|
DEFINE_PROP_LINK("downstream", TZMPC, downstream,
|
|
TYPE_MEMORY_REGION, MemoryRegion *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void tz_mpc_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = tz_mpc_realize;
|
|
dc->vmsd = &tz_mpc_vmstate;
|
|
dc->reset = tz_mpc_reset;
|
|
device_class_set_props(dc, tz_mpc_properties);
|
|
}
|
|
|
|
static const TypeInfo tz_mpc_info = {
|
|
.name = TYPE_TZ_MPC,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(TZMPC),
|
|
.instance_init = tz_mpc_init,
|
|
.class_init = tz_mpc_class_init,
|
|
};
|
|
|
|
static void tz_mpc_iommu_memory_region_class_init(ObjectClass *klass,
|
|
void *data)
|
|
{
|
|
IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
|
|
|
|
imrc->translate = tz_mpc_translate;
|
|
imrc->attrs_to_index = tz_mpc_attrs_to_index;
|
|
imrc->num_indexes = tz_mpc_num_indexes;
|
|
}
|
|
|
|
static const TypeInfo tz_mpc_iommu_memory_region_info = {
|
|
.name = TYPE_TZ_MPC_IOMMU_MEMORY_REGION,
|
|
.parent = TYPE_IOMMU_MEMORY_REGION,
|
|
.class_init = tz_mpc_iommu_memory_region_class_init,
|
|
};
|
|
|
|
static void tz_mpc_register_types(void)
|
|
{
|
|
type_register_static(&tz_mpc_info);
|
|
type_register_static(&tz_mpc_iommu_memory_region_info);
|
|
}
|
|
|
|
type_init(tz_mpc_register_types);
|