387 lines
10 KiB
C
387 lines
10 KiB
C
/*
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* QEMU National Semiconductor PC87312 (Super I/O)
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*
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* Copyright (c) 2010-2012 Herve Poussineau
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* Copyright (c) 2011-2012 Andreas Färber
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/isa/pc87312.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/module.h"
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#include "trace.h"
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#define REG_FER 0
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#define REG_FAR 1
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#define REG_PTR 2
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#define FER_PARALLEL_EN 0x01
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#define FER_UART1_EN 0x02
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#define FER_UART2_EN 0x04
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#define FER_FDC_EN 0x08
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#define FER_FDC_4 0x10
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#define FER_FDC_ADDR 0x20
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#define FER_IDE_EN 0x40
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#define FER_IDE_ADDR 0x80
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#define FAR_PARALLEL_ADDR 0x03
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#define FAR_UART1_ADDR 0x0C
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#define FAR_UART2_ADDR 0x30
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#define FAR_UART_3_4 0xC0
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#define PTR_POWER_DOWN 0x01
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#define PTR_CLOCK_DOWN 0x02
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#define PTR_PWDN 0x04
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#define PTR_IRQ_5_7 0x08
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#define PTR_UART1_TEST 0x10
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#define PTR_UART2_TEST 0x20
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#define PTR_LOCK_CONF 0x40
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#define PTR_EPP_MODE 0x80
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/* Parallel port */
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static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index)
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{
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PC87312State *s = PC87312(sio);
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return index ? false : s->regs[REG_FER] & FER_PARALLEL_EN;
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}
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static const uint16_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
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static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index)
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{
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PC87312State *s = PC87312(sio);
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return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
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}
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static const unsigned int parallel_irq[] = { 5, 7, 5, 0 };
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static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index)
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{
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PC87312State *s = PC87312(sio);
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int idx;
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idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
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if (idx == 0) {
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return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5;
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} else {
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return parallel_irq[idx];
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}
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}
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/* UARTs */
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static const uint16_t uart_base[2][4] = {
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{ 0x3e8, 0x338, 0x2e8, 0x220 },
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{ 0x2e8, 0x238, 0x2e0, 0x228 }
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};
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static uint16_t get_uart_iobase(ISASuperIODevice *sio, uint8_t i)
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{
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PC87312State *s = PC87312(sio);
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int idx;
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idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
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if (idx == 0) {
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return 0x3f8;
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} else if (idx == 1) {
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return 0x2f8;
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} else {
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return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6];
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}
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}
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static unsigned int get_uart_irq(ISASuperIODevice *sio, uint8_t i)
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{
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PC87312State *s = PC87312(sio);
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int idx;
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idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
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return (idx & 1) ? 3 : 4;
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}
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static bool is_uart_enabled(ISASuperIODevice *sio, uint8_t i)
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{
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PC87312State *s = PC87312(sio);
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return s->regs[REG_FER] & (FER_UART1_EN << i);
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}
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/* Floppy controller */
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static bool is_fdc_enabled(ISASuperIODevice *sio, uint8_t index)
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{
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PC87312State *s = PC87312(sio);
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assert(!index);
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return s->regs[REG_FER] & FER_FDC_EN;
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}
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static uint16_t get_fdc_iobase(ISASuperIODevice *sio, uint8_t index)
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{
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PC87312State *s = PC87312(sio);
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assert(!index);
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return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0;
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}
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static unsigned int get_fdc_irq(ISASuperIODevice *sio, uint8_t index)
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{
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assert(!index);
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return 6;
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}
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/* IDE controller */
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static bool is_ide_enabled(ISASuperIODevice *sio, uint8_t index)
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{
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PC87312State *s = PC87312(sio);
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return s->regs[REG_FER] & FER_IDE_EN;
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}
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static uint16_t get_ide_iobase(ISASuperIODevice *sio, uint8_t index)
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{
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PC87312State *s = PC87312(sio);
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if (index == 1) {
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return get_ide_iobase(sio, 0) + 0x206;
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}
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return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0;
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}
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static unsigned int get_ide_irq(ISASuperIODevice *sio, uint8_t index)
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{
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assert(index == 0);
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return 14;
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}
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static void reconfigure_devices(PC87312State *s)
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{
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error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)",
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s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]);
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}
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static void pc87312_soft_reset(PC87312State *s)
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{
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static const uint8_t fer_init[] = {
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0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b,
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0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f,
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0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07,
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0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00,
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};
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static const uint8_t far_init[] = {
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0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01,
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0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24,
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0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24,
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0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10,
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};
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static const uint8_t ptr_init[] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
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};
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s->read_id_step = 0;
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s->selected_index = REG_FER;
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s->regs[REG_FER] = fer_init[s->config & 0x1f];
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s->regs[REG_FAR] = far_init[s->config & 0x1f];
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s->regs[REG_PTR] = ptr_init[s->config & 0x1f];
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}
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static void pc87312_hard_reset(PC87312State *s)
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{
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pc87312_soft_reset(s);
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}
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static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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PC87312State *s = opaque;
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trace_pc87312_io_write(addr, val);
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if ((addr & 1) == 0) {
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/* Index register */
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s->read_id_step = 2;
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s->selected_index = val;
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} else {
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/* Data register */
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if (s->selected_index < 3) {
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s->regs[s->selected_index] = val;
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reconfigure_devices(s);
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}
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}
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}
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static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size)
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{
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PC87312State *s = opaque;
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uint32_t val;
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if ((addr & 1) == 0) {
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/* Index register */
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if (s->read_id_step++ == 0) {
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val = 0x88;
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} else if (s->read_id_step++ == 1) {
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val = 0;
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} else {
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val = s->selected_index;
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}
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} else {
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/* Data register */
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if (s->selected_index < 3) {
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val = s->regs[s->selected_index];
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} else {
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/* Invalid selected index */
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val = 0;
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}
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}
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trace_pc87312_io_read(addr, val);
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return val;
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}
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static const MemoryRegionOps pc87312_io_ops = {
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.read = pc87312_io_read,
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.write = pc87312_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static int pc87312_post_load(void *opaque, int version_id)
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{
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PC87312State *s = opaque;
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reconfigure_devices(s);
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return 0;
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}
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static void pc87312_reset(DeviceState *d)
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{
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PC87312State *s = PC87312(d);
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pc87312_soft_reset(s);
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}
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static void pc87312_realize(DeviceState *dev, Error **errp)
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{
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PC87312State *s;
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ISADevice *isa;
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Error *local_err = NULL;
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s = PC87312(dev);
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isa = ISA_DEVICE(dev);
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isa_register_ioport(isa, &s->io, s->iobase);
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pc87312_hard_reset(s);
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ISA_SUPERIO_GET_CLASS(dev)->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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}
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static void pc87312_initfn(Object *obj)
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{
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PC87312State *s = PC87312(obj);
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memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2);
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}
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static const VMStateDescription vmstate_pc87312 = {
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.name = "pc87312",
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.version_id = 1,
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.minimum_version_id = 1,
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.post_load = pc87312_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(read_id_step, PC87312State),
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VMSTATE_UINT8(selected_index, PC87312State),
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VMSTATE_UINT8_ARRAY(regs, PC87312State, 3),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property pc87312_properties[] = {
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DEFINE_PROP_UINT16("iobase", PC87312State, iobase, 0x398),
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DEFINE_PROP_UINT8("config", PC87312State, config, 1),
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DEFINE_PROP_END_OF_LIST()
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};
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static void pc87312_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
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sc->parent_realize = dc->realize;
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dc->realize = pc87312_realize;
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dc->reset = pc87312_reset;
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dc->vmsd = &vmstate_pc87312;
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device_class_set_props(dc, pc87312_properties);
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sc->parallel = (ISASuperIOFuncs){
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.count = 1,
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.is_enabled = is_parallel_enabled,
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.get_iobase = get_parallel_iobase,
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.get_irq = get_parallel_irq,
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};
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sc->serial = (ISASuperIOFuncs){
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.count = 2,
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.is_enabled = is_uart_enabled,
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.get_iobase = get_uart_iobase,
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.get_irq = get_uart_irq,
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};
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sc->floppy = (ISASuperIOFuncs){
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.count = 1,
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.is_enabled = is_fdc_enabled,
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.get_iobase = get_fdc_iobase,
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.get_irq = get_fdc_irq,
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};
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sc->ide = (ISASuperIOFuncs){
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.count = 1,
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.is_enabled = is_ide_enabled,
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.get_iobase = get_ide_iobase,
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.get_irq = get_ide_irq,
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};
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}
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static const TypeInfo pc87312_type_info = {
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.name = TYPE_PC87312,
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.parent = TYPE_ISA_SUPERIO,
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.instance_size = sizeof(PC87312State),
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.instance_init = pc87312_initfn,
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.class_init = pc87312_class_init,
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/* FIXME use a qdev drive property instead of drive_get() */
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};
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static void pc87312_register_types(void)
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{
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type_register_static(&pc87312_type_info);
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}
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type_init(pc87312_register_types)
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