279 lines
7 KiB
C
279 lines
7 KiB
C
/* Blackfin Core Timer model.
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Copyright (C) 2010-2022 Free Software Foundation, Inc.
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include "sim-main.h"
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#include "devices.h"
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#include "dv-bfin_cec.h"
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#include "dv-bfin_ctimer.h"
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struct bfin_ctimer
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{
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bu32 base;
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struct hw_event *handler;
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int64_t timeout;
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/* Order after here is important -- matches hardware MMR layout. */
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bu32 tcntl, tperiod, tscale, tcount;
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};
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#define mmr_base() offsetof(struct bfin_ctimer, tcntl)
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#define mmr_offset(mmr) (offsetof(struct bfin_ctimer, mmr) - mmr_base())
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static const char * const mmr_names[] =
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{
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"TCNTL", "TPERIOD", "TSCALE", "TCOUNT",
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};
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#define mmr_name(off) mmr_names[(off) / 4]
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static bool
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bfin_ctimer_enabled (struct bfin_ctimer *ctimer)
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{
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return (ctimer->tcntl & TMPWR) && (ctimer->tcntl & TMREN);
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}
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static bu32
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bfin_ctimer_scale (struct bfin_ctimer *ctimer)
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{
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/* Only low 8 bits are actually checked. */
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return (ctimer->tscale & 0xff) + 1;
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}
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static void
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bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer);
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static void
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bfin_ctimer_expire (struct hw *me, void *data)
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{
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struct bfin_ctimer *ctimer = data;
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ctimer->tcntl |= TINT;
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if (ctimer->tcntl & TAUTORLD)
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{
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ctimer->tcount = ctimer->tperiod;
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bfin_ctimer_schedule (me, ctimer);
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}
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else
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{
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ctimer->tcount = 0;
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ctimer->handler = NULL;
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}
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hw_port_event (me, IVG_IVTMR, 1);
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}
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static void
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bfin_ctimer_update_count (struct hw *me, struct bfin_ctimer *ctimer)
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{
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bu32 scale, ticks;
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int64_t timeout;
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/* If the timer was enabled w/out autoreload and has expired, then
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there's nothing to calculate here. */
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if (ctimer->handler == NULL)
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return;
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scale = bfin_ctimer_scale (ctimer);
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timeout = hw_event_remain_time (me, ctimer->handler);
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ticks = ctimer->timeout - timeout;
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ctimer->tcount -= (scale * ticks);
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ctimer->timeout = timeout;
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}
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static void
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bfin_ctimer_deschedule (struct hw *me, struct bfin_ctimer *ctimer)
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{
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if (ctimer->handler)
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{
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hw_event_queue_deschedule (me, ctimer->handler);
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ctimer->handler = NULL;
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}
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}
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static void
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bfin_ctimer_schedule (struct hw *me, struct bfin_ctimer *ctimer)
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{
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bu32 scale = bfin_ctimer_scale (ctimer);
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ctimer->timeout = (ctimer->tcount / scale) + !!(ctimer->tcount % scale);
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ctimer->handler = hw_event_queue_schedule (me, ctimer->timeout,
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bfin_ctimer_expire,
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ctimer);
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}
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static unsigned
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bfin_ctimer_io_write_buffer (struct hw *me, const void *source,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_ctimer *ctimer = hw_data (me);
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bool curr_enabled;
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bu32 mmr_off;
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bu32 value;
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bu32 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
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return 0;
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value = dv_load_4 (source);
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mmr_off = addr - ctimer->base;
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valuep = (void *)((uintptr_t)ctimer + mmr_base() + mmr_off);
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HW_TRACE_WRITE ();
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curr_enabled = bfin_ctimer_enabled (ctimer);
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switch (mmr_off)
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{
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case mmr_offset(tcntl):
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/* HRM describes TINT as sticky, but it isn't W1C. */
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*valuep = value;
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if (bfin_ctimer_enabled (ctimer) == curr_enabled)
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{
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/* Do nothing. */
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}
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else if (curr_enabled)
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{
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bfin_ctimer_update_count (me, ctimer);
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bfin_ctimer_deschedule (me, ctimer);
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}
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else
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bfin_ctimer_schedule (me, ctimer);
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break;
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case mmr_offset(tcount):
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/* HRM says writes are discarded when enabled. */
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/* XXX: But hardware seems to be writeable all the time ? */
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/* if (!curr_enabled) */
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*valuep = value;
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break;
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case mmr_offset(tperiod):
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/* HRM says writes are discarded when enabled. */
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/* XXX: But hardware seems to be writeable all the time ? */
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/* if (!curr_enabled) */
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{
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/* Writes are mirrored into TCOUNT. */
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ctimer->tcount = value;
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*valuep = value;
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}
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break;
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case mmr_offset(tscale):
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if (curr_enabled)
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{
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bfin_ctimer_update_count (me, ctimer);
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bfin_ctimer_deschedule (me, ctimer);
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}
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*valuep = value;
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if (curr_enabled)
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bfin_ctimer_schedule (me, ctimer);
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break;
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}
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return nr_bytes;
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}
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static unsigned
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bfin_ctimer_io_read_buffer (struct hw *me, void *dest,
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int space, address_word addr, unsigned nr_bytes)
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{
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struct bfin_ctimer *ctimer = hw_data (me);
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bu32 mmr_off;
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bu32 *valuep;
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/* Invalid access mode is higher priority than missing register. */
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if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
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return 0;
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mmr_off = addr - ctimer->base;
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valuep = (void *)((uintptr_t)ctimer + mmr_base() + mmr_off);
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HW_TRACE_READ ();
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switch (mmr_off)
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{
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case mmr_offset(tcount):
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/* Since we're optimizing events here, we need to calculate
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the new tcount value. */
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if (bfin_ctimer_enabled (ctimer))
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bfin_ctimer_update_count (me, ctimer);
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break;
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}
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dv_store_4 (dest, *valuep);
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return nr_bytes;
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}
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static const struct hw_port_descriptor bfin_ctimer_ports[] =
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{
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{ "ivtmr", IVG_IVTMR, 0, output_port, },
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{ NULL, 0, 0, 0, },
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};
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static void
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attach_bfin_ctimer_regs (struct hw *me, struct bfin_ctimer *ctimer)
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{
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address_word attach_address;
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int attach_space;
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unsigned attach_size;
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reg_property_spec reg;
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if (hw_find_property (me, "reg") == NULL)
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hw_abort (me, "Missing \"reg\" property");
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if (!hw_find_reg_array_property (me, "reg", 0, ®))
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hw_abort (me, "\"reg\" property must contain three addr/size entries");
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hw_unit_address_to_attach_address (hw_parent (me),
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®.address,
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&attach_space, &attach_address, me);
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hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me);
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if (attach_size != BFIN_COREMMR_CTIMER_SIZE)
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hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_CTIMER_SIZE);
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hw_attach_address (hw_parent (me),
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0, attach_space, attach_address, attach_size, me);
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ctimer->base = attach_address;
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}
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static void
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bfin_ctimer_finish (struct hw *me)
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{
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struct bfin_ctimer *ctimer;
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ctimer = HW_ZALLOC (me, struct bfin_ctimer);
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set_hw_data (me, ctimer);
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set_hw_io_read_buffer (me, bfin_ctimer_io_read_buffer);
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set_hw_io_write_buffer (me, bfin_ctimer_io_write_buffer);
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set_hw_ports (me, bfin_ctimer_ports);
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attach_bfin_ctimer_regs (me, ctimer);
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/* Initialize the Core Timer. */
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}
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const struct hw_descriptor dv_bfin_ctimer_descriptor[] =
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{
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{"bfin_ctimer", bfin_ctimer_finish,},
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{NULL, NULL},
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};
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