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/* tc-mt.c -- Assembler for the Morpho Technologies mt .
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Copyright (C) 2005-2022 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "as.h"
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#include "dwarf2dbg.h"
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#include "subsegs.h"
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#include "symcat.h"
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#include "opcodes/mt-desc.h"
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#include "opcodes/mt-opc.h"
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#include "cgen.h"
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#include "elf/common.h"
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#include "elf/mt.h"
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/* Structure to hold all of the different components
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describing an individual instruction. */
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typedef struct
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{
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const CGEN_INSN * insn;
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const CGEN_INSN * orig_insn;
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CGEN_FIELDS fields;
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#if CGEN_INT_INSN_P
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CGEN_INSN_INT buffer [1];
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#define INSN_VALUE(buf) (*(buf))
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#else
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unsigned char buffer [CGEN_MAX_INSN_SIZE];
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#define INSN_VALUE(buf) (buf)
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#endif
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char * addr;
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fragS * frag;
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int num_fixups;
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fixS * fixups [GAS_CGEN_MAX_FIXUPS];
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int indices [MAX_OPERAND_INSTANCES];
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}
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mt_insn;
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const char comment_chars[] = ";";
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const char line_comment_chars[] = "#";
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const char line_separator_chars[] = "";
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const char EXP_CHARS[] = "eE";
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const char FLT_CHARS[] = "dD";
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/* The target specific pseudo-ops which we support. */
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const pseudo_typeS md_pseudo_table[] =
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{
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{ "word", cons, 4 },
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{ NULL, NULL, 0 }
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};
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static int no_scheduling_restrictions = 0;
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struct option md_longopts[] =
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{
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#define OPTION_NO_SCHED_REST (OPTION_MD_BASE)
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{ "nosched", no_argument, NULL, OPTION_NO_SCHED_REST },
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#define OPTION_MARCH (OPTION_MD_BASE + 1)
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{ "march", required_argument, NULL, OPTION_MARCH},
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{ NULL, no_argument, NULL, 0 },
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};
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size_t md_longopts_size = sizeof (md_longopts);
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const char * md_shortopts = "";
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/* Mach selected from command line. */
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static int mt_mach = bfd_mach_ms1;
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static unsigned mt_mach_bitmask = 1 << MACH_MS1;
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/* Flags to set in the elf header */
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static flagword mt_flags = EF_MT_CPU_MRISC;
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/* The architecture to use. */
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enum mt_architectures
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{
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ms1_64_001,
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ms1_16_002,
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ms1_16_003,
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ms2
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};
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/* MT architecture we are using for this output file. */
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static enum mt_architectures mt_arch = ms1_16_002;
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int
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md_parse_option (int c ATTRIBUTE_UNUSED, const char * arg)
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{
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switch (c)
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{
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case OPTION_MARCH:
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if (strcmp (arg, "ms1-64-001") == 0)
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{
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mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC;
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mt_mach = bfd_mach_ms1;
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mt_mach_bitmask = 1 << MACH_MS1;
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mt_arch = ms1_64_001;
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}
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else if (strcmp (arg, "ms1-16-002") == 0)
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{
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mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC;
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mt_mach = bfd_mach_ms1;
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mt_mach_bitmask = 1 << MACH_MS1;
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mt_arch = ms1_16_002;
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}
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else if (strcmp (arg, "ms1-16-003") == 0)
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{
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mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MRISC2;
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mt_mach = bfd_mach_mrisc2;
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mt_mach_bitmask = 1 << MACH_MS1_003;
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mt_arch = ms1_16_003;
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}
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else if (strcmp (arg, "ms2") == 0)
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{
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mt_flags = (mt_flags & ~EF_MT_CPU_MASK) | EF_MT_CPU_MS2;
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mt_mach = bfd_mach_mrisc2;
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mt_mach_bitmask = 1 << MACH_MS2;
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mt_arch = ms2;
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}
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break;
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case OPTION_NO_SCHED_REST:
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no_scheduling_restrictions = 1;
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break;
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default:
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return 0;
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}
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return 1;
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}
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void
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md_show_usage (FILE * stream)
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{
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fprintf (stream, _("MT specific command line options:\n"));
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fprintf (stream, _(" -march=ms1-64-001 allow ms1-64-001 instructions\n"));
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fprintf (stream, _(" -march=ms1-16-002 allow ms1-16-002 instructions (default)\n"));
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fprintf (stream, _(" -march=ms1-16-003 allow ms1-16-003 instructions\n"));
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fprintf (stream, _(" -march=ms2 allow ms2 instructions \n"));
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fprintf (stream, _(" -nosched disable scheduling restrictions\n"));
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}
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void
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md_begin (void)
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{
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/* Initialize the `cgen' interface. */
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/* Set the machine number and endian. */
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gas_cgen_cpu_desc = mt_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, mt_mach_bitmask,
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CGEN_CPU_OPEN_ENDIAN,
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CGEN_ENDIAN_BIG,
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CGEN_CPU_OPEN_END);
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mt_cgen_init_asm (gas_cgen_cpu_desc);
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/* This is a callback from cgen to gas to parse operands. */
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cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
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/* Set the ELF flags if desired. */
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if (mt_flags)
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bfd_set_private_flags (stdoutput, mt_flags);
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/* Set the machine type. */
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bfd_default_set_arch_mach (stdoutput, bfd_arch_mt, mt_mach);
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literal_prefix_dollar_hex = true;
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}
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void
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md_assemble (char * str)
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{
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static long delayed_load_register = 0;
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static long prev_delayed_load_register = 0;
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static int last_insn_had_delay_slot = 0;
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static int last_insn_in_noncond_delay_slot = 0;
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static int last_insn_has_load_delay = 0;
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static int last_insn_was_memory_access = 0;
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static int last_insn_was_io_insn = 0;
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static int last_insn_was_arithmetic_or_logic = 0;
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static int last_insn_was_branch_insn = 0;
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static int last_insn_was_conditional_branch_insn = 0;
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mt_insn insn;
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char * errmsg;
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/* Initialize GAS's cgen interface for a new instruction. */
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gas_cgen_init_parse ();
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insn.insn = mt_cgen_assemble_insn
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(gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
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if (!insn.insn)
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{
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as_bad ("%s", errmsg);
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return;
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}
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/* Doesn't really matter what we pass for RELAX_P here. */
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gas_cgen_finish_insn (insn.insn, insn.buffer,
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CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
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/* Handle Scheduling Restrictions. */
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if (!no_scheduling_restrictions)
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{
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/* Detect consecutive Memory Accesses. */
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if (last_insn_was_memory_access
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&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS)
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&& mt_mach == ms1_64_001)
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as_warn (_("instruction %s may not follow another memory access instruction."),
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CGEN_INSN_NAME (insn.insn));
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/* Detect consecutive I/O Instructions. */
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else if (last_insn_was_io_insn
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&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN))
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as_warn (_("instruction %s may not follow another I/O instruction."),
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CGEN_INSN_NAME (insn.insn));
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/* Detect consecutive branch instructions. */
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else if (last_insn_was_branch_insn
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&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN))
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as_warn (_("%s may not occupy the delay slot of another branch insn."),
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CGEN_INSN_NAME (insn.insn));
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/* Detect data dependencies on delayed loads: memory and input insns. */
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if (last_insn_has_load_delay && delayed_load_register)
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{
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if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
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&& insn.fields.f_sr1 == delayed_load_register)
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as_warn (_("operand references R%ld of previous load."),
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insn.fields.f_sr1);
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if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
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&& insn.fields.f_sr2 == delayed_load_register)
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as_warn (_("operand references R%ld of previous load."),
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insn.fields.f_sr2);
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}
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/* Detect JAL/RETI hazard */
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if (mt_mach == ms2
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&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_JAL_HAZARD))
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{
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if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
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&& insn.fields.f_sr1 == delayed_load_register)
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|| (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
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&& insn.fields.f_sr2 == delayed_load_register))
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as_warn (_("operand references R%ld of previous instruction."),
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delayed_load_register);
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else if ((CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
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&& insn.fields.f_sr1 == prev_delayed_load_register)
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|| (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
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&& insn.fields.f_sr2 == prev_delayed_load_register))
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as_warn (_("operand references R%ld of instruction before previous."),
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prev_delayed_load_register);
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}
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/* Detect data dependency between conditional branch instruction
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and an immediately preceding arithmetic or logical instruction. */
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if (last_insn_was_arithmetic_or_logic
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&& !last_insn_in_noncond_delay_slot
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&& (delayed_load_register != 0)
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&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
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&& mt_arch == ms1_64_001)
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{
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if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
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&& insn.fields.f_sr1 == delayed_load_register)
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as_warn (_("conditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn."),
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insn.fields.f_sr1);
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if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
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&& insn.fields.f_sr2 == delayed_load_register)
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as_warn (_("conditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn."),
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insn.fields.f_sr2);
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}
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}
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/* Keep track of details of this insn for processing next insn. */
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last_insn_in_noncond_delay_slot = last_insn_was_branch_insn
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&& !last_insn_was_conditional_branch_insn;
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last_insn_had_delay_slot =
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CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
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(void) last_insn_had_delay_slot;
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last_insn_has_load_delay =
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CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_LOAD_DELAY);
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last_insn_was_memory_access =
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CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS);
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last_insn_was_io_insn =
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CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN);
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last_insn_was_arithmetic_or_logic =
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CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_AL_INSN);
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last_insn_was_branch_insn =
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CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN);
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last_insn_was_conditional_branch_insn =
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CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
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&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2);
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prev_delayed_load_register = delayed_load_register;
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if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR))
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delayed_load_register = insn.fields.f_dr;
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else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR))
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delayed_load_register = insn.fields.f_drrr;
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else /* Insns has no destination register. */
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delayed_load_register = 0;
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/* Generate dwarf2 line numbers. */
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dwarf2_emit_insn (4);
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}
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valueT
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md_section_align (segT segment, valueT size)
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{
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int align = bfd_section_alignment (segment);
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return ((size + (1 << align) - 1) & -(1 << align));
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}
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symbolS *
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md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
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{
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return NULL;
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}
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int
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md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
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segT segment ATTRIBUTE_UNUSED)
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{
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as_fatal (_("md_estimate_size_before_relax\n"));
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return 1;
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}
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/* *fragP has been relaxed to its final size, and now needs to have
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the bytes inside it modified to conform to the new size.
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Called after relaxation is finished.
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fragP->fr_type == rs_machine_dependent.
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fragP->fr_subtype is the subtype of what the address relaxed to. */
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void
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md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED,
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segT sec ATTRIBUTE_UNUSED,
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fragS * fragP ATTRIBUTE_UNUSED)
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{
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}
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/* Functions concerning relocs. */
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long
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md_pcrel_from_section (fixS *fixP, segT sec)
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{
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if (fixP->fx_addsy != (symbolS *) NULL
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&& (!S_IS_DEFINED (fixP->fx_addsy)
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|| S_GET_SEGMENT (fixP->fx_addsy) != sec))
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/* The symbol is undefined (or is defined but not in this section).
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Let the linker figure it out. */
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return 0;
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/* Return the address of the opcode - cgen adjusts for opcode size
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itself, to be consistent with the disassembler, which must do
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so. */
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return fixP->fx_where + fixP->fx_frag->fr_address;
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}
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/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
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Returns BFD_RELOC_NONE if no reloc type can be found.
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*FIXP may be modified if desired. */
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bfd_reloc_code_real_type
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md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED,
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|
const CGEN_OPERAND * operand,
|
|
|
fixS * fixP ATTRIBUTE_UNUSED)
|
|
|
{
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|
|
bfd_reloc_code_real_type result;
|
|
|
|
|
|
result = BFD_RELOC_NONE;
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|
|
|
|
|
switch (operand->type)
|
|
|
{
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|
|
case MT_OPERAND_IMM16O:
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|
|
result = BFD_RELOC_16_PCREL;
|
|
|
fixP->fx_pcrel = 1;
|
|
|
/* fixP->fx_no_overflow = 1; */
|
|
|
break;
|
|
|
case MT_OPERAND_IMM16:
|
|
|
case MT_OPERAND_IMM16Z:
|
|
|
/* These may have been processed at parse time. */
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|
|
if (fixP->fx_cgen.opinfo != 0)
|
|
|
result = fixP->fx_cgen.opinfo;
|
|
|
fixP->fx_no_overflow = 1;
|
|
|
break;
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|
|
case MT_OPERAND_LOOPSIZE:
|
|
|
result = BFD_RELOC_MT_PCINSN8;
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|
|
fixP->fx_pcrel = 1;
|
|
|
/* Adjust for the delay slot, which is not part of the loop */
|
|
|
fixP->fx_offset -= 8;
|
|
|
break;
|
|
|
default:
|
|
|
result = BFD_RELOC_NONE;
|
|
|
break;
|
|
|
}
|
|
|
|
|
|
return result;
|
|
|
}
|
|
|
|
|
|
/* Write a value out to the object file, using the appropriate endianness. */
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|
|
|
|
|
void
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|
|
md_number_to_chars (char * buf, valueT val, int n)
|
|
|
{
|
|
|
number_to_chars_bigendian (buf, val, n);
|
|
|
}
|
|
|
|
|
|
const char *
|
|
|
md_atof (int type, char * litP, int * sizeP)
|
|
|
{
|
|
|
return ieee_md_atof (type, litP, sizeP, false);
|
|
|
}
|
|
|
|
|
|
/* See whether we need to force a relocation into the output file. */
|
|
|
|
|
|
int
|
|
|
mt_force_relocation (fixS * fixp ATTRIBUTE_UNUSED)
|
|
|
{
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
void
|
|
|
mt_apply_fix (fixS *fixP, valueT *valueP, segT seg)
|
|
|
{
|
|
|
if ((fixP->fx_pcrel != 0) && (fixP->fx_r_type == BFD_RELOC_32))
|
|
|
fixP->fx_r_type = BFD_RELOC_32_PCREL;
|
|
|
|
|
|
gas_cgen_md_apply_fix (fixP, valueP, seg);
|
|
|
}
|
|
|
|
|
|
bool
|
|
|
mt_fix_adjustable (fixS * fixP)
|
|
|
{
|
|
|
if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
|
|
|
{
|
|
|
const CGEN_INSN *insn = NULL;
|
|
|
int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
|
|
|
const CGEN_OPERAND *operand;
|
|
|
|
|
|
operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
|
|
|
md_cgen_lookup_reloc (insn, operand, fixP);
|
|
|
}
|
|
|
|
|
|
if (fixP->fx_addsy == NULL)
|
|
|
return true;
|
|
|
|
|
|
/* Prevent all adjustments to global symbols. */
|
|
|
if (S_IS_EXTERNAL (fixP->fx_addsy))
|
|
|
return false;
|
|
|
|
|
|
if (S_IS_WEAK (fixP->fx_addsy))
|
|
|
return false;
|
|
|
|
|
|
return true;
|
|
|
}
|