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/* Native-dependent code for GNU/Linux AArch64.
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Copyright (C) 2011-2022 Free Software Foundation, Inc.
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Contributed by ARM Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "inferior.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "linux-nat.h"
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#include "target-descriptions.h"
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#include "auxv.h"
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#include "gdbcmd.h"
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#include "aarch64-nat.h"
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#include "aarch64-tdep.h"
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#include "aarch64-linux-tdep.h"
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#include "aarch32-linux-nat.h"
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#include "aarch32-tdep.h"
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#include "arch/arm.h"
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#include "nat/aarch64-linux.h"
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#include "nat/aarch64-linux-hw-point.h"
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#include "nat/aarch64-sve-linux-ptrace.h"
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#include "elf/external.h"
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#include "elf/common.h"
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#include "nat/gdb_ptrace.h"
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#include <sys/utsname.h>
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#include <asm/ptrace.h>
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#include "gregset.h"
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#include "linux-tdep.h"
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#include "arm-tdep.h"
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/* Defines ps_err_e, struct ps_prochandle. */
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#include "gdb_proc_service.h"
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#include "arch-utils.h"
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#include "arch/aarch64-mte-linux.h"
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#include "nat/aarch64-mte-linux-ptrace.h"
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#ifndef TRAP_HWBKPT
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#define TRAP_HWBKPT 0x0004
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#endif
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class aarch64_linux_nat_target final
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: public aarch64_nat_target<linux_nat_target>
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{
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public:
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/* Add our register access methods. */
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void fetch_registers (struct regcache *, int) override;
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void store_registers (struct regcache *, int) override;
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const struct target_desc *read_description () override;
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/* Add our hardware breakpoint and watchpoint implementation. */
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bool stopped_by_watchpoint () override;
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bool stopped_data_address (CORE_ADDR *) override;
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int can_do_single_step () override;
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/* Override the GNU/Linux inferior startup hook. */
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void post_startup_inferior (ptid_t) override;
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/* Override the GNU/Linux post attach hook. */
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void post_attach (int pid) override;
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/* These three defer to common nat/ code. */
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void low_new_thread (struct lwp_info *lp) override
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{ aarch64_linux_new_thread (lp); }
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void low_delete_thread (struct arch_lwp_info *lp) override
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{ aarch64_linux_delete_thread (lp); }
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void low_prepare_to_resume (struct lwp_info *lp) override
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{ aarch64_linux_prepare_to_resume (lp); }
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void low_new_fork (struct lwp_info *parent, pid_t child_pid) override;
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void low_forget_process (pid_t pid) override;
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/* Add our siginfo layout converter. */
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bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
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override;
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struct gdbarch *thread_architecture (ptid_t) override;
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bool supports_memory_tagging () override;
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/* Read memory allocation tags from memory via PTRACE. */
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bool fetch_memtags (CORE_ADDR address, size_t len,
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gdb::byte_vector &tags, int type) override;
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/* Write allocation tags to memory via PTRACE. */
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bool store_memtags (CORE_ADDR address, size_t len,
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const gdb::byte_vector &tags, int type) override;
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};
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static aarch64_linux_nat_target the_aarch64_linux_nat_target;
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/* Called whenever GDB is no longer debugging process PID. It deletes
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data structures that keep track of debug register state. */
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void
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aarch64_linux_nat_target::low_forget_process (pid_t pid)
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{
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aarch64_remove_debug_reg_state (pid);
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}
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/* Fill GDB's register array with the general-purpose register values
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from the current thread. */
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static void
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fetch_gregs_from_thread (struct regcache *regcache)
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{
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int ret, tid;
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struct gdbarch *gdbarch = regcache->arch ();
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elf_gregset_t regs;
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struct iovec iovec;
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/* Make sure REGS can hold all registers contents on both aarch64
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and arm. */
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gdb_static_assert (sizeof (regs) >= 18 * 4);
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tid = regcache->ptid ().lwp ();
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iovec.iov_base = ®s;
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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iovec.iov_len = 18 * 4;
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else
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iovec.iov_len = sizeof (regs);
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ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to fetch general registers"));
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1);
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else
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{
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int regno;
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for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
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regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]);
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}
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}
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/* Store to the current thread the valid general-purpose register
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values in the GDB's register array. */
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static void
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store_gregs_to_thread (const struct regcache *regcache)
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{
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int ret, tid;
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elf_gregset_t regs;
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struct iovec iovec;
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struct gdbarch *gdbarch = regcache->arch ();
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/* Make sure REGS can hold all registers contents on both aarch64
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and arm. */
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gdb_static_assert (sizeof (regs) >= 18 * 4);
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tid = regcache->ptid ().lwp ();
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iovec.iov_base = ®s;
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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iovec.iov_len = 18 * 4;
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else
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iovec.iov_len = sizeof (regs);
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ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to fetch general registers"));
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1);
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else
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{
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int regno;
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for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
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if (REG_VALID == regcache->get_register_status (regno))
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regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]);
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}
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ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to store general registers"));
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}
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/* Fill GDB's register array with the fp/simd register values
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from the current thread. */
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static void
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fetch_fpregs_from_thread (struct regcache *regcache)
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{
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int ret, tid;
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elf_fpregset_t regs;
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struct iovec iovec;
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struct gdbarch *gdbarch = regcache->arch ();
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/* Make sure REGS can hold all VFP registers contents on both aarch64
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and arm. */
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gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
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tid = regcache->ptid ().lwp ();
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iovec.iov_base = ®s;
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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{
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iovec.iov_len = ARM_VFP3_REGS_SIZE;
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ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to fetch VFP registers"));
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aarch32_vfp_regcache_supply (regcache, (gdb_byte *) ®s, 32);
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}
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else
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{
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int regno;
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iovec.iov_len = sizeof (regs);
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ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to fetch vFP/SIMD registers"));
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for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
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regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]);
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regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr);
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regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr);
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}
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}
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/* Store to the current thread the valid fp/simd register
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values in the GDB's register array. */
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static void
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store_fpregs_to_thread (const struct regcache *regcache)
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{
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int ret, tid;
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elf_fpregset_t regs;
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struct iovec iovec;
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struct gdbarch *gdbarch = regcache->arch ();
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/* Make sure REGS can hold all VFP registers contents on both aarch64
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and arm. */
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gdb_static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
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tid = regcache->ptid ().lwp ();
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iovec.iov_base = ®s;
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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{
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iovec.iov_len = ARM_VFP3_REGS_SIZE;
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ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to fetch VFP registers"));
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aarch32_vfp_regcache_collect (regcache, (gdb_byte *) ®s, 32);
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}
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else
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{
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int regno;
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iovec.iov_len = sizeof (regs);
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ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to fetch FP/SIMD registers"));
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for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
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if (REG_VALID == regcache->get_register_status (regno))
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regcache->raw_collect
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(regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]);
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if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM))
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regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr);
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if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM))
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regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr);
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}
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if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
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{
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ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to store VFP registers"));
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}
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else
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{
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ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to store FP/SIMD registers"));
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}
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}
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/* Fill GDB's register array with the sve register values
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from the current thread. */
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static void
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fetch_sveregs_from_thread (struct regcache *regcache)
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{
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std::unique_ptr<gdb_byte[]> base
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= aarch64_sve_get_sveregs (regcache->ptid ().lwp ());
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aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ());
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}
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/* Store to the current thread the valid sve register
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values in the GDB's register array. */
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static void
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store_sveregs_to_thread (struct regcache *regcache)
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{
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int ret;
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struct iovec iovec;
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int tid = regcache->ptid ().lwp ();
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/* First store vector length to the thread. This is done first to ensure the
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ptrace buffers read from the kernel are the correct size. */
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if (!aarch64_sve_set_vq (tid, regcache))
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perror_with_name (_("Unable to set VG register"));
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/* Obtain a dump of SVE registers from ptrace. */
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std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid);
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/* Overwrite with regcache state. */
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aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ());
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/* Write back to the kernel. */
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iovec.iov_base = base.get ();
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iovec.iov_len = ((struct user_sve_header *) base.get ())->size;
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ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec);
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if (ret < 0)
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perror_with_name (_("Unable to store sve registers"));
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}
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/* Fill GDB's register array with the pointer authentication mask values from
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the current thread. */
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static void
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fetch_pauth_masks_from_thread (struct regcache *regcache)
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{
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aarch64_gdbarch_tdep *tdep
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= (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
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int ret;
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struct iovec iovec;
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uint64_t pauth_regset[2] = {0, 0};
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int tid = regcache->ptid ().lwp ();
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iovec.iov_base = &pauth_regset;
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iovec.iov_len = sizeof (pauth_regset);
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ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec);
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if (ret != 0)
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perror_with_name (_("unable to fetch pauth registers"));
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regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base),
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&pauth_regset[0]);
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regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base),
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&pauth_regset[1]);
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}
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/* Fill GDB's register array with the MTE register values from
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the current thread. */
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static void
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fetch_mteregs_from_thread (struct regcache *regcache)
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{
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aarch64_gdbarch_tdep *tdep
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= (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
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int regno = tdep->mte_reg_base;
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gdb_assert (regno != -1);
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uint64_t tag_ctl = 0;
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struct iovec iovec;
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iovec.iov_base = &tag_ctl;
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iovec.iov_len = sizeof (tag_ctl);
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int tid = get_ptrace_pid (regcache->ptid ());
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if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
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perror_with_name (_("unable to fetch MTE registers"));
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regcache->raw_supply (regno, &tag_ctl);
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}
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/* Store to the current thread the valid MTE register set in the GDB's
|
|
|
register array. */
|
|
|
|
|
|
static void
|
|
|
store_mteregs_to_thread (struct regcache *regcache)
|
|
|
{
|
|
|
aarch64_gdbarch_tdep *tdep
|
|
|
= (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
|
|
|
int regno = tdep->mte_reg_base;
|
|
|
|
|
|
gdb_assert (regno != -1);
|
|
|
|
|
|
uint64_t tag_ctl = 0;
|
|
|
|
|
|
if (REG_VALID != regcache->get_register_status (regno))
|
|
|
return;
|
|
|
|
|
|
regcache->raw_collect (regno, (char *) &tag_ctl);
|
|
|
|
|
|
struct iovec iovec;
|
|
|
|
|
|
iovec.iov_base = &tag_ctl;
|
|
|
iovec.iov_len = sizeof (tag_ctl);
|
|
|
|
|
|
int tid = get_ptrace_pid (regcache->ptid ());
|
|
|
if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
|
|
|
perror_with_name (_("unable to store MTE registers"));
|
|
|
}
|
|
|
|
|
|
/* Fill GDB's register array with the TLS register values from
|
|
|
the current thread. */
|
|
|
|
|
|
static void
|
|
|
fetch_tlsregs_from_thread (struct regcache *regcache)
|
|
|
{
|
|
|
aarch64_gdbarch_tdep *tdep
|
|
|
= (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
|
|
|
int regno = tdep->tls_regnum;
|
|
|
|
|
|
gdb_assert (regno != -1);
|
|
|
|
|
|
uint64_t tpidr = 0;
|
|
|
struct iovec iovec;
|
|
|
|
|
|
iovec.iov_base = &tpidr;
|
|
|
iovec.iov_len = sizeof (tpidr);
|
|
|
|
|
|
int tid = get_ptrace_pid (regcache->ptid ());
|
|
|
if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
|
|
|
perror_with_name (_("unable to fetch TLS register"));
|
|
|
|
|
|
regcache->raw_supply (regno, &tpidr);
|
|
|
}
|
|
|
|
|
|
/* Store to the current thread the valid TLS register set in GDB's
|
|
|
register array. */
|
|
|
|
|
|
static void
|
|
|
store_tlsregs_to_thread (struct regcache *regcache)
|
|
|
{
|
|
|
aarch64_gdbarch_tdep *tdep
|
|
|
= (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
|
|
|
int regno = tdep->tls_regnum;
|
|
|
|
|
|
gdb_assert (regno != -1);
|
|
|
|
|
|
uint64_t tpidr = 0;
|
|
|
|
|
|
if (REG_VALID != regcache->get_register_status (regno))
|
|
|
return;
|
|
|
|
|
|
regcache->raw_collect (regno, (char *) &tpidr);
|
|
|
|
|
|
struct iovec iovec;
|
|
|
|
|
|
iovec.iov_base = &tpidr;
|
|
|
iovec.iov_len = sizeof (tpidr);
|
|
|
|
|
|
int tid = get_ptrace_pid (regcache->ptid ());
|
|
|
if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
|
|
|
perror_with_name (_("unable to store TLS register"));
|
|
|
}
|
|
|
|
|
|
/* The AArch64 version of the "fetch_registers" target_ops method. Fetch
|
|
|
REGNO from the target and place the result into REGCACHE. */
|
|
|
|
|
|
static void
|
|
|
aarch64_fetch_registers (struct regcache *regcache, int regno)
|
|
|
{
|
|
|
aarch64_gdbarch_tdep *tdep
|
|
|
= (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
|
|
|
|
|
|
if (regno == -1)
|
|
|
{
|
|
|
fetch_gregs_from_thread (regcache);
|
|
|
if (tdep->has_sve ())
|
|
|
fetch_sveregs_from_thread (regcache);
|
|
|
else
|
|
|
fetch_fpregs_from_thread (regcache);
|
|
|
|
|
|
if (tdep->has_pauth ())
|
|
|
fetch_pauth_masks_from_thread (regcache);
|
|
|
|
|
|
if (tdep->has_mte ())
|
|
|
fetch_mteregs_from_thread (regcache);
|
|
|
|
|
|
if (tdep->has_tls ())
|
|
|
fetch_tlsregs_from_thread (regcache);
|
|
|
}
|
|
|
else if (regno < AARCH64_V0_REGNUM)
|
|
|
fetch_gregs_from_thread (regcache);
|
|
|
else if (tdep->has_sve ())
|
|
|
fetch_sveregs_from_thread (regcache);
|
|
|
else
|
|
|
fetch_fpregs_from_thread (regcache);
|
|
|
|
|
|
if (tdep->has_pauth ())
|
|
|
{
|
|
|
if (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
|
|
|
|| regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base))
|
|
|
fetch_pauth_masks_from_thread (regcache);
|
|
|
}
|
|
|
|
|
|
/* Fetch individual MTE registers. */
|
|
|
if (tdep->has_mte ()
|
|
|
&& (regno == tdep->mte_reg_base))
|
|
|
fetch_mteregs_from_thread (regcache);
|
|
|
|
|
|
if (tdep->has_tls () && regno == tdep->tls_regnum)
|
|
|
fetch_tlsregs_from_thread (regcache);
|
|
|
}
|
|
|
|
|
|
/* A version of the "fetch_registers" target_ops method used when running
|
|
|
32-bit ARM code on an AArch64 target. Fetch REGNO from the target and
|
|
|
place the result into REGCACHE. */
|
|
|
|
|
|
static void
|
|
|
aarch32_fetch_registers (struct regcache *regcache, int regno)
|
|
|
{
|
|
|
arm_gdbarch_tdep *tdep
|
|
|
= (arm_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
|
|
|
|
|
|
if (regno == -1)
|
|
|
{
|
|
|
fetch_gregs_from_thread (regcache);
|
|
|
if (tdep->vfp_register_count > 0)
|
|
|
fetch_fpregs_from_thread (regcache);
|
|
|
}
|
|
|
else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
|
|
|
fetch_gregs_from_thread (regcache);
|
|
|
else if (tdep->vfp_register_count > 0
|
|
|
&& regno >= ARM_D0_REGNUM
|
|
|
&& (regno < ARM_D0_REGNUM + tdep->vfp_register_count
|
|
|
|| regno == ARM_FPSCR_REGNUM))
|
|
|
fetch_fpregs_from_thread (regcache);
|
|
|
}
|
|
|
|
|
|
/* Implement the "fetch_registers" target_ops method. */
|
|
|
|
|
|
void
|
|
|
aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
|
|
|
int regno)
|
|
|
{
|
|
|
if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
|
|
|
aarch32_fetch_registers (regcache, regno);
|
|
|
else
|
|
|
aarch64_fetch_registers (regcache, regno);
|
|
|
}
|
|
|
|
|
|
/* The AArch64 version of the "store_registers" target_ops method. Copy
|
|
|
the value of register REGNO from REGCACHE into the the target. */
|
|
|
|
|
|
static void
|
|
|
aarch64_store_registers (struct regcache *regcache, int regno)
|
|
|
{
|
|
|
aarch64_gdbarch_tdep *tdep
|
|
|
= (aarch64_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
|
|
|
|
|
|
if (regno == -1)
|
|
|
{
|
|
|
store_gregs_to_thread (regcache);
|
|
|
if (tdep->has_sve ())
|
|
|
store_sveregs_to_thread (regcache);
|
|
|
else
|
|
|
store_fpregs_to_thread (regcache);
|
|
|
|
|
|
if (tdep->has_mte ())
|
|
|
store_mteregs_to_thread (regcache);
|
|
|
|
|
|
if (tdep->has_tls ())
|
|
|
store_tlsregs_to_thread (regcache);
|
|
|
}
|
|
|
else if (regno < AARCH64_V0_REGNUM)
|
|
|
store_gregs_to_thread (regcache);
|
|
|
else if (tdep->has_sve ())
|
|
|
store_sveregs_to_thread (regcache);
|
|
|
else
|
|
|
store_fpregs_to_thread (regcache);
|
|
|
|
|
|
/* Store MTE registers. */
|
|
|
if (tdep->has_mte ()
|
|
|
&& (regno == tdep->mte_reg_base))
|
|
|
store_mteregs_to_thread (regcache);
|
|
|
|
|
|
if (tdep->has_tls () && regno == tdep->tls_regnum)
|
|
|
store_tlsregs_to_thread (regcache);
|
|
|
}
|
|
|
|
|
|
/* A version of the "store_registers" target_ops method used when running
|
|
|
32-bit ARM code on an AArch64 target. Copy the value of register REGNO
|
|
|
from REGCACHE into the the target. */
|
|
|
|
|
|
static void
|
|
|
aarch32_store_registers (struct regcache *regcache, int regno)
|
|
|
{
|
|
|
arm_gdbarch_tdep *tdep
|
|
|
= (arm_gdbarch_tdep *) gdbarch_tdep (regcache->arch ());
|
|
|
|
|
|
if (regno == -1)
|
|
|
{
|
|
|
store_gregs_to_thread (regcache);
|
|
|
if (tdep->vfp_register_count > 0)
|
|
|
store_fpregs_to_thread (regcache);
|
|
|
}
|
|
|
else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
|
|
|
store_gregs_to_thread (regcache);
|
|
|
else if (tdep->vfp_register_count > 0
|
|
|
&& regno >= ARM_D0_REGNUM
|
|
|
&& (regno < ARM_D0_REGNUM + tdep->vfp_register_count
|
|
|
|| regno == ARM_FPSCR_REGNUM))
|
|
|
store_fpregs_to_thread (regcache);
|
|
|
}
|
|
|
|
|
|
/* Implement the "store_registers" target_ops method. */
|
|
|
|
|
|
void
|
|
|
aarch64_linux_nat_target::store_registers (struct regcache *regcache,
|
|
|
int regno)
|
|
|
{
|
|
|
if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
|
|
|
aarch32_store_registers (regcache, regno);
|
|
|
else
|
|
|
aarch64_store_registers (regcache, regno);
|
|
|
}
|
|
|
|
|
|
/* Fill register REGNO (if it is a general-purpose register) in
|
|
|
*GREGSETPS with the value in GDB's register array. If REGNO is -1,
|
|
|
do this for all registers. */
|
|
|
|
|
|
void
|
|
|
fill_gregset (const struct regcache *regcache,
|
|
|
gdb_gregset_t *gregsetp, int regno)
|
|
|
{
|
|
|
regcache_collect_regset (&aarch64_linux_gregset, regcache,
|
|
|
regno, (gdb_byte *) gregsetp,
|
|
|
AARCH64_LINUX_SIZEOF_GREGSET);
|
|
|
}
|
|
|
|
|
|
/* Fill GDB's register array with the general-purpose register values
|
|
|
in *GREGSETP. */
|
|
|
|
|
|
void
|
|
|
supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
|
|
|
{
|
|
|
regcache_supply_regset (&aarch64_linux_gregset, regcache, -1,
|
|
|
(const gdb_byte *) gregsetp,
|
|
|
AARCH64_LINUX_SIZEOF_GREGSET);
|
|
|
}
|
|
|
|
|
|
/* Fill register REGNO (if it is a floating-point register) in
|
|
|
*FPREGSETP with the value in GDB's register array. If REGNO is -1,
|
|
|
do this for all registers. */
|
|
|
|
|
|
void
|
|
|
fill_fpregset (const struct regcache *regcache,
|
|
|
gdb_fpregset_t *fpregsetp, int regno)
|
|
|
{
|
|
|
regcache_collect_regset (&aarch64_linux_fpregset, regcache,
|
|
|
regno, (gdb_byte *) fpregsetp,
|
|
|
AARCH64_LINUX_SIZEOF_FPREGSET);
|
|
|
}
|
|
|
|
|
|
/* Fill GDB's register array with the floating-point register values
|
|
|
in *FPREGSETP. */
|
|
|
|
|
|
void
|
|
|
supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
|
|
|
{
|
|
|
regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1,
|
|
|
(const gdb_byte *) fpregsetp,
|
|
|
AARCH64_LINUX_SIZEOF_FPREGSET);
|
|
|
}
|
|
|
|
|
|
/* linux_nat_new_fork hook. */
|
|
|
|
|
|
void
|
|
|
aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent,
|
|
|
pid_t child_pid)
|
|
|
{
|
|
|
pid_t parent_pid;
|
|
|
struct aarch64_debug_reg_state *parent_state;
|
|
|
struct aarch64_debug_reg_state *child_state;
|
|
|
|
|
|
/* NULL means no watchpoint has ever been set in the parent. In
|
|
|
that case, there's nothing to do. */
|
|
|
if (parent->arch_private == NULL)
|
|
|
return;
|
|
|
|
|
|
/* GDB core assumes the child inherits the watchpoints/hw
|
|
|
breakpoints of the parent, and will remove them all from the
|
|
|
forked off process. Copy the debug registers mirrors into the
|
|
|
new process so that all breakpoints and watchpoints can be
|
|
|
removed together. */
|
|
|
|
|
|
parent_pid = parent->ptid.pid ();
|
|
|
parent_state = aarch64_get_debug_reg_state (parent_pid);
|
|
|
child_state = aarch64_get_debug_reg_state (child_pid);
|
|
|
*child_state = *parent_state;
|
|
|
}
|
|
|
|
|
|
|
|
|
/* Called by libthread_db. Returns a pointer to the thread local
|
|
|
storage (or its descriptor). */
|
|
|
|
|
|
ps_err_e
|
|
|
ps_get_thread_area (struct ps_prochandle *ph,
|
|
|
lwpid_t lwpid, int idx, void **base)
|
|
|
{
|
|
|
int is_64bit_p
|
|
|
= (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64);
|
|
|
|
|
|
return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p);
|
|
|
}
|
|
|
|
|
|
|
|
|
/* Implement the virtual inf_ptrace_target::post_startup_inferior method. */
|
|
|
|
|
|
void
|
|
|
aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid)
|
|
|
{
|
|
|
low_forget_process (ptid.pid ());
|
|
|
aarch64_linux_get_debug_reg_capacity (ptid.pid ());
|
|
|
linux_nat_target::post_startup_inferior (ptid);
|
|
|
}
|
|
|
|
|
|
/* Implement the "post_attach" target_ops method. */
|
|
|
|
|
|
void
|
|
|
aarch64_linux_nat_target::post_attach (int pid)
|
|
|
{
|
|
|
low_forget_process (pid);
|
|
|
/* Set the hardware debug register capacity. If
|
|
|
aarch64_linux_get_debug_reg_capacity is not called
|
|
|
(as it is in aarch64_linux_child_post_startup_inferior) then
|
|
|
software watchpoints will be used instead of hardware
|
|
|
watchpoints when attaching to a target. */
|
|
|
aarch64_linux_get_debug_reg_capacity (pid);
|
|
|
linux_nat_target::post_attach (pid);
|
|
|
}
|
|
|
|
|
|
/* Implement the "read_description" target_ops method. */
|
|
|
|
|
|
const struct target_desc *
|
|
|
aarch64_linux_nat_target::read_description ()
|
|
|
{
|
|
|
int ret, tid;
|
|
|
gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
|
|
|
struct iovec iovec;
|
|
|
|
|
|
tid = inferior_ptid.pid ();
|
|
|
|
|
|
iovec.iov_base = regbuf;
|
|
|
iovec.iov_len = ARM_VFP3_REGS_SIZE;
|
|
|
|
|
|
ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
|
|
|
if (ret == 0)
|
|
|
return aarch32_read_description ();
|
|
|
|
|
|
CORE_ADDR hwcap = linux_get_hwcap (this);
|
|
|
CORE_ADDR hwcap2 = linux_get_hwcap2 (this);
|
|
|
|
|
|
aarch64_features features;
|
|
|
features.vq = aarch64_sve_get_vq (tid);
|
|
|
features.pauth = hwcap & AARCH64_HWCAP_PACA;
|
|
|
features.mte = hwcap2 & HWCAP2_MTE;
|
|
|
features.tls = true;
|
|
|
|
|
|
return aarch64_read_description (features);
|
|
|
}
|
|
|
|
|
|
/* Convert a native/host siginfo object, into/from the siginfo in the
|
|
|
layout of the inferiors' architecture. Returns true if any
|
|
|
conversion was done; false otherwise. If DIRECTION is 1, then copy
|
|
|
from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to
|
|
|
INF. */
|
|
|
|
|
|
bool
|
|
|
aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf,
|
|
|
int direction)
|
|
|
{
|
|
|
struct gdbarch *gdbarch = get_frame_arch (get_current_frame ());
|
|
|
|
|
|
/* Is the inferior 32-bit? If so, then do fixup the siginfo
|
|
|
object. */
|
|
|
if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
|
|
|
{
|
|
|
if (direction == 0)
|
|
|
aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf,
|
|
|
native);
|
|
|
else
|
|
|
aarch64_siginfo_from_compat_siginfo (native,
|
|
|
(struct compat_siginfo *) inf);
|
|
|
|
|
|
return true;
|
|
|
}
|
|
|
|
|
|
return false;
|
|
|
}
|
|
|
|
|
|
/* Implement the "stopped_data_address" target_ops method. */
|
|
|
|
|
|
bool
|
|
|
aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
|
|
|
{
|
|
|
siginfo_t siginfo;
|
|
|
struct aarch64_debug_reg_state *state;
|
|
|
|
|
|
if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
|
|
|
return false;
|
|
|
|
|
|
/* This must be a hardware breakpoint. */
|
|
|
if (siginfo.si_signo != SIGTRAP
|
|
|
|| (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
|
|
|
return false;
|
|
|
|
|
|
/* Make sure to ignore the top byte, otherwise we may not recognize a
|
|
|
hardware watchpoint hit. The stopped data addresses coming from the
|
|
|
kernel can potentially be tagged addresses. */
|
|
|
struct gdbarch *gdbarch = thread_architecture (inferior_ptid);
|
|
|
const CORE_ADDR addr_trap
|
|
|
= address_significant (gdbarch, (CORE_ADDR) siginfo.si_addr);
|
|
|
|
|
|
/* Check if the address matches any watched address. */
|
|
|
state = aarch64_get_debug_reg_state (inferior_ptid.pid ());
|
|
|
return aarch64_stopped_data_address (state, addr_trap, addr_p);
|
|
|
}
|
|
|
|
|
|
/* Implement the "stopped_by_watchpoint" target_ops method. */
|
|
|
|
|
|
bool
|
|
|
aarch64_linux_nat_target::stopped_by_watchpoint ()
|
|
|
{
|
|
|
CORE_ADDR addr;
|
|
|
|
|
|
return stopped_data_address (&addr);
|
|
|
}
|
|
|
|
|
|
/* Implement the "can_do_single_step" target_ops method. */
|
|
|
|
|
|
int
|
|
|
aarch64_linux_nat_target::can_do_single_step ()
|
|
|
{
|
|
|
return 1;
|
|
|
}
|
|
|
|
|
|
/* Implement the "thread_architecture" target_ops method.
|
|
|
|
|
|
Returns the gdbarch for the thread identified by PTID. If the thread in
|
|
|
question is a 32-bit ARM thread, then the architecture returned will be
|
|
|
that of the process itself.
|
|
|
|
|
|
If the thread is an AArch64 thread then we need to check the current
|
|
|
vector length; if the vector length has changed then we need to lookup a
|
|
|
new gdbarch that matches the new vector length. */
|
|
|
|
|
|
struct gdbarch *
|
|
|
aarch64_linux_nat_target::thread_architecture (ptid_t ptid)
|
|
|
{
|
|
|
/* Find the current gdbarch the same way as process_stratum_target. */
|
|
|
inferior *inf = find_inferior_ptid (this, ptid);
|
|
|
gdb_assert (inf != NULL);
|
|
|
|
|
|
/* If this is a 32-bit architecture, then this is ARM, not AArch64.
|
|
|
There's no SVE vectors here, so just return the inferior
|
|
|
architecture. */
|
|
|
if (gdbarch_bfd_arch_info (inf->gdbarch)->bits_per_word == 32)
|
|
|
return inf->gdbarch;
|
|
|
|
|
|
/* Only return it if the current vector length matches the one in the tdep. */
|
|
|
aarch64_gdbarch_tdep *tdep
|
|
|
= (aarch64_gdbarch_tdep *) gdbarch_tdep (inf->gdbarch);
|
|
|
uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
|
|
|
if (vq == tdep->vq)
|
|
|
return inf->gdbarch;
|
|
|
|
|
|
/* We reach here if the vector length for the thread is different from its
|
|
|
value at process start. Lookup gdbarch via info (potentially creating a
|
|
|
new one), stashing the vector length inside id. Use -1 for when SVE
|
|
|
unavailable, to distinguish from an unset value of 0. */
|
|
|
struct gdbarch_info info;
|
|
|
info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
|
|
|
info.id = (int *) (vq == 0 ? -1 : vq);
|
|
|
return gdbarch_find_by_info (info);
|
|
|
}
|
|
|
|
|
|
/* Implement the "supports_memory_tagging" target_ops method. */
|
|
|
|
|
|
bool
|
|
|
aarch64_linux_nat_target::supports_memory_tagging ()
|
|
|
{
|
|
|
return (linux_get_hwcap2 (this) & HWCAP2_MTE) != 0;
|
|
|
}
|
|
|
|
|
|
/* Implement the "fetch_memtags" target_ops method. */
|
|
|
|
|
|
bool
|
|
|
aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address, size_t len,
|
|
|
gdb::byte_vector &tags, int type)
|
|
|
{
|
|
|
int tid = get_ptrace_pid (inferior_ptid);
|
|
|
|
|
|
/* Allocation tags? */
|
|
|
if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
|
|
|
return aarch64_mte_fetch_memtags (tid, address, len, tags);
|
|
|
|
|
|
return false;
|
|
|
}
|
|
|
|
|
|
/* Implement the "store_memtags" target_ops method. */
|
|
|
|
|
|
bool
|
|
|
aarch64_linux_nat_target::store_memtags (CORE_ADDR address, size_t len,
|
|
|
const gdb::byte_vector &tags, int type)
|
|
|
{
|
|
|
int tid = get_ptrace_pid (inferior_ptid);
|
|
|
|
|
|
/* Allocation tags? */
|
|
|
if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
|
|
|
return aarch64_mte_store_memtags (tid, address, len, tags);
|
|
|
|
|
|
return false;
|
|
|
}
|
|
|
|
|
|
void _initialize_aarch64_linux_nat ();
|
|
|
void
|
|
|
_initialize_aarch64_linux_nat ()
|
|
|
{
|
|
|
aarch64_initialize_hw_point ();
|
|
|
|
|
|
/* Register the target. */
|
|
|
linux_target = &the_aarch64_linux_nat_target;
|
|
|
add_inf_child_target (&the_aarch64_linux_nat_target);
|
|
|
}
|