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759 lines
82 KiB
Plaintext
759 lines
82 KiB
Plaintext
Timing Analyzer report for test
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Thu Mar 9 12:26:36 2023
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Quartus Prime Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Parallel Compilation
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4. Clocks
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5. Slow 1100mV 85C Model Fmax Summary
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6. Timing Closure Recommendations
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7. Slow 1100mV 85C Model Setup Summary
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8. Slow 1100mV 85C Model Hold Summary
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9. Slow 1100mV 85C Model Recovery Summary
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10. Slow 1100mV 85C Model Removal Summary
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11. Slow 1100mV 85C Model Minimum Pulse Width Summary
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12. Slow 1100mV 85C Model Metastability Summary
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13. Slow 1100mV 0C Model Fmax Summary
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14. Slow 1100mV 0C Model Setup Summary
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15. Slow 1100mV 0C Model Hold Summary
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16. Slow 1100mV 0C Model Recovery Summary
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17. Slow 1100mV 0C Model Removal Summary
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18. Slow 1100mV 0C Model Minimum Pulse Width Summary
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19. Slow 1100mV 0C Model Metastability Summary
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20. Fast 1100mV 85C Model Setup Summary
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21. Fast 1100mV 85C Model Hold Summary
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22. Fast 1100mV 85C Model Recovery Summary
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23. Fast 1100mV 85C Model Removal Summary
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24. Fast 1100mV 85C Model Minimum Pulse Width Summary
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25. Fast 1100mV 85C Model Metastability Summary
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26. Fast 1100mV 0C Model Setup Summary
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27. Fast 1100mV 0C Model Hold Summary
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28. Fast 1100mV 0C Model Recovery Summary
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29. Fast 1100mV 0C Model Removal Summary
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30. Fast 1100mV 0C Model Minimum Pulse Width Summary
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31. Fast 1100mV 0C Model Metastability Summary
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32. Multicorner Timing Analysis Summary
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33. Board Trace Model Assignments
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34. Input Transition Times
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35. Signal Integrity Metrics (Slow 1100mv 0c Model)
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36. Signal Integrity Metrics (Slow 1100mv 85c Model)
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37. Signal Integrity Metrics (Fast 1100mv 0c Model)
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38. Signal Integrity Metrics (Fast 1100mv 85c Model)
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39. Setup Transfers
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40. Hold Transfers
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41. Recovery Transfers
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42. Removal Transfers
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43. Report TCCS
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44. Report RSKM
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45. Unconstrained Paths Summary
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46. Clock Status Summary
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47. Unconstrained Input Ports
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48. Unconstrained Output Ports
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49. Unconstrained Input Ports
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50. Unconstrained Output Ports
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51. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2022 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and any partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details, at
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https://fpgasoftware.intel.com/eula.
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+------------------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+-----------------------+------------------------------------------------------------+
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; Quartus Prime Version ; Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition ;
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; Timing Analyzer ; Legacy Timing Analyzer ;
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; Revision Name ; test ;
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; Device Family ; Cyclone V ;
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; Device Name ; 5CSEMA5F31C6 ;
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; Timing Models ; Final ;
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; Delay Model ; Combined ;
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; Rise/Fall Delays ; Enabled ;
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+-----------------------+------------------------------------------------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 6 ;
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; Maximum allowed ; 6 ;
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; ; ;
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; Average used ; 2.55 ;
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; Maximum used ; 6 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 34.4% ;
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; Processor 3 ; 34.3% ;
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; Processor 4 ; 34.1% ;
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; Processor 5 ; 26.3% ;
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; Processor 6 ; 26.3% ;
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+----------------------------+-------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clocks ;
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+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
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; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
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+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
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; clk_i ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk_i } ;
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+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
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+--------------------------------------------------+
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; Slow 1100mV 85C Model Fmax Summary ;
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+------------+-----------------+------------+------+
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; Fmax ; Restricted Fmax ; Clock Name ; Note ;
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+------------+-----------------+------------+------+
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; 127.26 MHz ; 127.26 MHz ; clk_i ; ;
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+------------+-----------------+------------+------+
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This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
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----------------------------------
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; Timing Closure Recommendations ;
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----------------------------------
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HTML report is unavailable in plain text report export.
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+-------------------------------------+
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; Slow 1100mV 85C Model Setup Summary ;
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+-------+--------+--------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+--------------------+
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; clk_i ; -6.858 ; -29693.859 ;
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+-------+--------+--------------------+
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+------------------------------------+
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; Slow 1100mV 85C Model Hold Summary ;
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+-------+-------+--------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+--------------------+
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; clk_i ; 0.289 ; 0.000 ;
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+-------+-------+--------------------+
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+----------------------------------------+
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; Slow 1100mV 85C Model Recovery Summary ;
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+-------+--------+-----------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+-----------------------+
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; clk_i ; -2.655 ; -2072.473 ;
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+-------+--------+-----------------------+
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+---------------------------------------+
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; Slow 1100mV 85C Model Removal Summary ;
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+-------+-------+-----------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+-----------------------+
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; clk_i ; 1.096 ; 0.000 ;
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+-------+-------+-----------------------+
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+---------------------------------------------------+
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; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
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+-------+--------+----------------------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+----------------------------------+
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; clk_i ; -2.636 ; -24567.597 ;
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+-------+--------+----------------------------------+
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-----------------------------------------------
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; Slow 1100mV 85C Model Metastability Summary ;
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-----------------------------------------------
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Design MTBF is not calculated because the design doesn't meet its timing requirements.
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+--------------------------------------------------+
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; Slow 1100mV 0C Model Fmax Summary ;
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+------------+-----------------+------------+------+
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; Fmax ; Restricted Fmax ; Clock Name ; Note ;
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+------------+-----------------+------------+------+
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; 130.23 MHz ; 130.23 MHz ; clk_i ; ;
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+------------+-----------------+------------+------+
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This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
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+------------------------------------+
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; Slow 1100mV 0C Model Setup Summary ;
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+-------+--------+-------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+-------------------+
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; clk_i ; -6.679 ; -28699.615 ;
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+-------+--------+-------------------+
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+-----------------------------------+
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; Slow 1100mV 0C Model Hold Summary ;
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+-------+-------+-------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+-------------------+
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; clk_i ; 0.277 ; 0.000 ;
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+-------+-------+-------------------+
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+---------------------------------------+
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; Slow 1100mV 0C Model Recovery Summary ;
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+-------+--------+----------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+----------------------+
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; clk_i ; -2.418 ; -1856.336 ;
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+-------+--------+----------------------+
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+--------------------------------------+
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; Slow 1100mV 0C Model Removal Summary ;
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+-------+-------+----------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+----------------------+
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; clk_i ; 0.997 ; 0.000 ;
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+-------+-------+----------------------+
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+--------------------------------------------------+
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; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
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+-------+--------+---------------------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+---------------------------------+
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; clk_i ; -2.636 ; -24427.626 ;
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+-------+--------+---------------------------------+
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----------------------------------------------
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; Slow 1100mV 0C Model Metastability Summary ;
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----------------------------------------------
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Design MTBF is not calculated because the design doesn't meet its timing requirements.
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+-------------------------------------+
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; Fast 1100mV 85C Model Setup Summary ;
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+-------+--------+--------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+--------------------+
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; clk_i ; -3.793 ; -15390.058 ;
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+-------+--------+--------------------+
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+------------------------------------+
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; Fast 1100mV 85C Model Hold Summary ;
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+-------+-------+--------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+--------------------+
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; clk_i ; 0.167 ; 0.000 ;
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+-------+-------+--------------------+
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+----------------------------------------+
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; Fast 1100mV 85C Model Recovery Summary ;
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+-------+--------+-----------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+-----------------------+
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; clk_i ; -1.987 ; -1545.265 ;
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+-------+--------+-----------------------+
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+---------------------------------------+
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; Fast 1100mV 85C Model Removal Summary ;
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+-------+-------+-----------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+-----------------------+
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; clk_i ; 1.244 ; 0.000 ;
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+-------+-------+-----------------------+
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+---------------------------------------------------+
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; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
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+-------+--------+----------------------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+----------------------------------+
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; clk_i ; -2.636 ; -24474.017 ;
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+-------+--------+----------------------------------+
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-----------------------------------------------
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; Fast 1100mV 85C Model Metastability Summary ;
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-----------------------------------------------
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Design MTBF is not calculated because the design doesn't meet its timing requirements.
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+------------------------------------+
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; Fast 1100mV 0C Model Setup Summary ;
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+-------+--------+-------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+-------------------+
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; clk_i ; -3.319 ; -13002.365 ;
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+-------+--------+-------------------+
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+-----------------------------------+
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; Fast 1100mV 0C Model Hold Summary ;
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+-------+-------+-------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+-------------------+
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; clk_i ; 0.156 ; 0.000 ;
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+-------+-------+-------------------+
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+---------------------------------------+
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; Fast 1100mV 0C Model Recovery Summary ;
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+-------+--------+----------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+----------------------+
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; clk_i ; -1.814 ; -1444.593 ;
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+-------+--------+----------------------+
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+--------------------------------------+
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; Fast 1100mV 0C Model Removal Summary ;
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+-------+-------+----------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+----------------------+
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; clk_i ; 1.277 ; 0.000 ;
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+-------+-------+----------------------+
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+--------------------------------------------------+
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; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
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+-------+--------+---------------------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+---------------------------------+
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; clk_i ; -2.636 ; -24952.821 ;
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+-------+--------+---------------------------------+
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----------------------------------------------
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; Fast 1100mV 0C Model Metastability Summary ;
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----------------------------------------------
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Design MTBF is not calculated because the design doesn't meet its timing requirements.
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+-----------------------------------------------------------------------------------+
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; Multicorner Timing Analysis Summary ;
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+------------------+------------+-------+-----------+---------+---------------------+
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; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
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+------------------+------------+-------+-----------+---------+---------------------+
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; Worst-case Slack ; -6.858 ; 0.156 ; -2.655 ; 0.997 ; -2.636 ;
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; clk_i ; -6.858 ; 0.156 ; -2.655 ; 0.997 ; -2.636 ;
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; Design-wide TNS ; -29693.859 ; 0.0 ; -2072.473 ; 0.0 ; -24952.821 ;
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; clk_i ; -29693.859 ; 0.000 ; -2072.473 ; 0.000 ; -24952.821 ;
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+------------------+------------+-------+-----------+---------+---------------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Board Trace Model Assignments ;
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+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
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+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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; gpio_o[0] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; gpio_o[1] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; gpio_o[2] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; gpio_o[3] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; gpio_o[4] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; gpio_o[5] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; gpio_o[6] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; gpio_o[7] ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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; uart0_txd_o ; 3.3-V LVCMOS ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
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+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
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+----------------------------------------------------------------+
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; Input Transition Times ;
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+-------------+--------------+-----------------+-----------------+
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; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
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+-------------+--------------+-----------------+-----------------+
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; clk_i ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
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; rstn_i ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
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; uart0_rxd_i ; 3.3-V LVCMOS ; 2640 ps ; 2640 ps ;
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+-------------+--------------+-----------------+-----------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
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+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
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+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
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; gpio_o[0] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
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; gpio_o[1] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
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; gpio_o[2] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
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|
; gpio_o[3] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
|
|
; gpio_o[4] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
|
|
; gpio_o[5] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
|
|
; gpio_o[6] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ; 3.08 V ; 2.62e-07 V ; 3.1 V ; -0.153 V ; 0.035 V ; 0.31 V ; 4.23e-10 s ; 1.59e-10 s ; Yes ; No ;
|
|
; gpio_o[7] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
|
|
; uart0_txd_o ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ; 3.08 V ; 3.5e-07 V ; 3.14 V ; -0.195 V ; 0.158 V ; 0.394 V ; 4.46e-10 s ; 1.64e-10 s ; Yes ; No ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; gpio_o[0] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
|
|
; gpio_o[1] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
|
|
; gpio_o[2] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
|
|
; gpio_o[3] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
|
|
; gpio_o[4] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
|
|
; gpio_o[5] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
|
|
; gpio_o[6] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ; 3.08 V ; 2.61e-05 V ; 3.09 V ; -0.0638 V ; 0.034 V ; 0.099 V ; 5.12e-10 s ; 2.97e-10 s ; Yes ; Yes ;
|
|
; gpio_o[7] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
|
|
; uart0_txd_o ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ; 3.08 V ; 3.32e-05 V ; 3.09 V ; -0.11 V ; 0.031 V ; 0.155 V ; 5.43e-10 s ; 3.14e-10 s ; Yes ; Yes ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; gpio_o[0] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
|
|
; gpio_o[1] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
|
|
; gpio_o[2] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
|
|
; gpio_o[3] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
|
|
; gpio_o[4] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
|
|
; gpio_o[5] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
|
|
; gpio_o[6] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ; 3.63 V ; 3.63e-06 V ; 3.64 V ; -0.326 V ; 0.091 V ; 0.479 V ; 3.83e-10 s ; 1.5e-10 s ; Yes ; No ;
|
|
; gpio_o[7] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
|
|
; uart0_txd_o ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ; 3.63 V ; 4.94e-06 V ; 3.69 V ; -0.414 V ; 0.134 V ; 0.585 V ; 4.19e-10 s ; 1.53e-10 s ; Yes ; No ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
; gpio_o[0] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
|
|
; gpio_o[1] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
|
|
; gpio_o[2] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
|
|
; gpio_o[3] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
|
|
; gpio_o[4] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
|
|
; gpio_o[5] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
|
|
; gpio_o[6] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ; 3.63 V ; 0.000184 V ; 3.64 V ; -0.19 V ; 0.019 V ; 0.425 V ; 4.44e-10 s ; 1.91e-10 s ; Yes ; No ;
|
|
; gpio_o[7] ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
|
|
; uart0_txd_o ; 3.3-V LVCMOS ; 0 s ; 0 s ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ; 3.63 V ; 0.000238 V ; 3.64 V ; -0.254 V ; 0.052 V ; 0.543 V ; 4.59e-10 s ; 1.96e-10 s ; Yes ; No ;
|
|
+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
|
|
|
|
|
+-------------------------------------------------------------------+
|
|
; Setup Transfers ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; clk_i ; clk_i ; 524105 ; 0 ; 0 ; 8 ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
+-------------------------------------------------------------------+
|
|
; Hold Transfers ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; clk_i ; clk_i ; 524105 ; 0 ; 0 ; 8 ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
+-------------------------------------------------------------------+
|
|
; Recovery Transfers ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; clk_i ; clk_i ; 0 ; 1063 ; 0 ; 0 ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
+-------------------------------------------------------------------+
|
|
; Removal Transfers ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
; clk_i ; clk_i ; 0 ; 1063 ; 0 ; 0 ;
|
|
+------------+----------+----------+----------+----------+----------+
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
|
|
|
|
|
---------------
|
|
; Report TCCS ;
|
|
---------------
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
|
|
|
|
|
---------------
|
|
; Report RSKM ;
|
|
---------------
|
|
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
|
|
|
|
|
|
+------------------------------------------------+
|
|
; Unconstrained Paths Summary ;
|
|
+---------------------------------+-------+------+
|
|
; Property ; Setup ; Hold ;
|
|
+---------------------------------+-------+------+
|
|
; Illegal Clocks ; 0 ; 0 ;
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
|
; Unconstrained Input Ports ; 2 ; 2 ;
|
|
; Unconstrained Input Port Paths ; 8 ; 8 ;
|
|
; Unconstrained Output Ports ; 9 ; 9 ;
|
|
; Unconstrained Output Port Paths ; 9 ; 9 ;
|
|
+---------------------------------+-------+------+
|
|
|
|
|
|
+-------------------------------------+
|
|
; Clock Status Summary ;
|
|
+--------+-------+------+-------------+
|
|
; Target ; Clock ; Type ; Status ;
|
|
+--------+-------+------+-------------+
|
|
; clk_i ; clk_i ; Base ; Constrained ;
|
|
+--------+-------+------+-------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Input Ports ;
|
|
+-------------+--------------------------------------------------------------------------------------+
|
|
; Input Port ; Comment ;
|
|
+-------------+--------------------------------------------------------------------------------------+
|
|
; rstn_i ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; uart0_rxd_i ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+--------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Output Ports ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; Output Port ; Comment ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; gpio_o[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; uart0_txd_o ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Input Ports ;
|
|
+-------------+--------------------------------------------------------------------------------------+
|
|
; Input Port ; Comment ;
|
|
+-------------+--------------------------------------------------------------------------------------+
|
|
; rstn_i ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; uart0_rxd_i ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
+-------------+--------------------------------------------------------------------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------+
|
|
; Unconstrained Output Ports ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; Output Port ; Comment ;
|
|
+-------------+---------------------------------------------------------------------------------------+
|
|
; gpio_o[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
|
|
; gpio_o[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
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|
; gpio_o[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
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|
; gpio_o[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
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|
; gpio_o[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
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|
; gpio_o[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
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|
; gpio_o[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
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|
; uart0_txd_o ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
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+-------------+---------------------------------------------------------------------------------------+
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+--------------------------+
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; Timing Analyzer Messages ;
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+--------------------------+
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Info: *******************************************************************
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Info: Running Quartus Prime Timing Analyzer
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Info: Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition
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Info: Processing started: Thu Mar 9 12:26:27 2023
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Info: Command: quartus_sta bootloarder_1 -c test
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Info: qsta_default_script.tcl version: #1
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Warning (20013): Ignored 24 assignments for entity "gfsdg" -- entity does not exist in design
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Warning (20014): Assignment for entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES OFF -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST OFF -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_COLOR 16764057 -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -entity gfsdg -section_id Top was ignored
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|
Warning (20014): Assignment for entity set_global_assignment -name ALLOW_MULTIPLE_PERSONAS OFF -entity gfsdg -section_id Top was ignored
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|
Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ASD_REGION_ID 1 -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS OFF -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_INPUTS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name MERGE_EQUIVALENT_BIDIRS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_EXTRACT_HARD_BLOCK_NODES ON -entity gfsdg -section_id Top was ignored
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Warning (20014): Assignment for entity set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION OFF -entity gfsdg -section_id Top was ignored
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
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Info (21077): Low junction temperature is 0 degrees C
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Info (21077): High junction temperature is 85 degrees C
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Critical Warning (332012): Synopsys Design Constraints File file not found: 'test.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
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Info (332105): Deriving Clocks
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Info (332105): create_clock -period 1.000 -name clk_i clk_i
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Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
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Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
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|
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
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|
Info: Analyzing Slow 1100mV 85C Model
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Critical Warning (332148): Timing requirements not met
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
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|
Info (332146): Worst-case setup slack is -6.858
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|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -6.858 -29693.859 clk_i
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Info (332146): Worst-case hold slack is 0.289
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|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.289 0.000 clk_i
|
|
Info (332146): Worst-case recovery slack is -2.655
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -2.655 -2072.473 clk_i
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|
Info (332146): Worst-case removal slack is 1.096
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 1.096 0.000 clk_i
|
|
Info (332146): Worst-case minimum pulse width slack is -2.636
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -2.636 -24567.597 clk_i
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|
Info (332114): Report Metastability: Found 1 synchronizer chains.
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|
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
|
|
Info: Analyzing Slow 1100mV 0C Model
|
|
Info (334003): Started post-fitting delay annotation
|
|
Info (334004): Delay annotation completed successfully
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
|
|
Critical Warning (332148): Timing requirements not met
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
|
|
Info (332146): Worst-case setup slack is -6.679
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -6.679 -28699.615 clk_i
|
|
Info (332146): Worst-case hold slack is 0.277
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.277 0.000 clk_i
|
|
Info (332146): Worst-case recovery slack is -2.418
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -2.418 -1856.336 clk_i
|
|
Info (332146): Worst-case removal slack is 0.997
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.997 0.000 clk_i
|
|
Info (332146): Worst-case minimum pulse width slack is -2.636
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -2.636 -24427.626 clk_i
|
|
Info (332114): Report Metastability: Found 1 synchronizer chains.
|
|
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
|
|
Info: Analyzing Fast 1100mV 85C Model
|
|
Info (334003): Started post-fitting delay annotation
|
|
Info (334004): Delay annotation completed successfully
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
|
|
Critical Warning (332148): Timing requirements not met
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
|
|
Info (332146): Worst-case setup slack is -3.793
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -3.793 -15390.058 clk_i
|
|
Info (332146): Worst-case hold slack is 0.167
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.167 0.000 clk_i
|
|
Info (332146): Worst-case recovery slack is -1.987
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -1.987 -1545.265 clk_i
|
|
Info (332146): Worst-case removal slack is 1.244
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 1.244 0.000 clk_i
|
|
Info (332146): Worst-case minimum pulse width slack is -2.636
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -2.636 -24474.017 clk_i
|
|
Info (332114): Report Metastability: Found 1 synchronizer chains.
|
|
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
|
|
Info: Analyzing Fast 1100mV 0C Model
|
|
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
|
|
Critical Warning (332148): Timing requirements not met
|
|
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the Timing Analyzer.
|
|
Info (332146): Worst-case setup slack is -3.319
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -3.319 -13002.365 clk_i
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|
Info (332146): Worst-case hold slack is 0.156
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 0.156 0.000 clk_i
|
|
Info (332146): Worst-case recovery slack is -1.814
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -1.814 -1444.593 clk_i
|
|
Info (332146): Worst-case removal slack is 1.277
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): 1.277 0.000 clk_i
|
|
Info (332146): Worst-case minimum pulse width slack is -2.636
|
|
Info (332119): Slack End Point TNS Clock
|
|
Info (332119): ========= =================== =====================
|
|
Info (332119): -2.636 -24952.821 clk_i
|
|
Info (332114): Report Metastability: Found 1 synchronizer chains.
|
|
Info (332114): Design MTBF is not calculated because the design doesn't meet its timing requirements.
|
|
Info (332102): Design is not fully constrained for setup requirements
|
|
Info (332102): Design is not fully constrained for hold requirements
|
|
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 31 warnings
|
|
Info: Peak virtual memory: 979 megabytes
|
|
Info: Processing ended: Thu Mar 9 12:26:36 2023
|
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Info: Elapsed time: 00:00:09
|
|
Info: Total CPU time (on all processors): 00:00:19
|
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