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89 lines
5.0 KiB
Plaintext
89 lines
5.0 KiB
Plaintext
--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel
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--VERSION_BEGIN 22.1 cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC VERSION_END
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-- Copyright (C) 2022 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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--synthesis_resources = lut 8
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SUBDESIGN mux_ofb
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(
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data[31..0] : input;
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result[7..0] : output;
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sel[1..0] : input;
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)
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VARIABLE
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l1_w0_n0_mux_dataout : WIRE;
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l1_w0_n1_mux_dataout : WIRE;
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l1_w1_n0_mux_dataout : WIRE;
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l1_w1_n1_mux_dataout : WIRE;
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l1_w2_n0_mux_dataout : WIRE;
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l1_w2_n1_mux_dataout : WIRE;
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l1_w3_n0_mux_dataout : WIRE;
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l1_w3_n1_mux_dataout : WIRE;
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l1_w4_n0_mux_dataout : WIRE;
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l1_w4_n1_mux_dataout : WIRE;
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l1_w5_n0_mux_dataout : WIRE;
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l1_w5_n1_mux_dataout : WIRE;
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l1_w6_n0_mux_dataout : WIRE;
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l1_w6_n1_mux_dataout : WIRE;
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l1_w7_n0_mux_dataout : WIRE;
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l1_w7_n1_mux_dataout : WIRE;
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l2_w0_n0_mux_dataout : WIRE;
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l2_w1_n0_mux_dataout : WIRE;
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l2_w2_n0_mux_dataout : WIRE;
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l2_w3_n0_mux_dataout : WIRE;
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l2_w4_n0_mux_dataout : WIRE;
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l2_w5_n0_mux_dataout : WIRE;
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l2_w6_n0_mux_dataout : WIRE;
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l2_w7_n0_mux_dataout : WIRE;
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data_wire[47..0] : WIRE;
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result_wire_ext[7..0] : WIRE;
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sel_wire[3..0] : WIRE;
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BEGIN
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l1_w0_n0_mux_dataout = sel_wire[0..0] & data_wire[8..8] # !(sel_wire[0..0]) & data_wire[0..0];
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l1_w0_n1_mux_dataout = sel_wire[0..0] & data_wire[24..24] # !(sel_wire[0..0]) & data_wire[16..16];
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l1_w1_n0_mux_dataout = sel_wire[0..0] & data_wire[9..9] # !(sel_wire[0..0]) & data_wire[1..1];
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l1_w1_n1_mux_dataout = sel_wire[0..0] & data_wire[25..25] # !(sel_wire[0..0]) & data_wire[17..17];
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l1_w2_n0_mux_dataout = sel_wire[0..0] & data_wire[10..10] # !(sel_wire[0..0]) & data_wire[2..2];
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l1_w2_n1_mux_dataout = sel_wire[0..0] & data_wire[26..26] # !(sel_wire[0..0]) & data_wire[18..18];
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l1_w3_n0_mux_dataout = sel_wire[0..0] & data_wire[11..11] # !(sel_wire[0..0]) & data_wire[3..3];
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l1_w3_n1_mux_dataout = sel_wire[0..0] & data_wire[27..27] # !(sel_wire[0..0]) & data_wire[19..19];
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l1_w4_n0_mux_dataout = sel_wire[0..0] & data_wire[12..12] # !(sel_wire[0..0]) & data_wire[4..4];
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l1_w4_n1_mux_dataout = sel_wire[0..0] & data_wire[28..28] # !(sel_wire[0..0]) & data_wire[20..20];
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l1_w5_n0_mux_dataout = sel_wire[0..0] & data_wire[13..13] # !(sel_wire[0..0]) & data_wire[5..5];
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l1_w5_n1_mux_dataout = sel_wire[0..0] & data_wire[29..29] # !(sel_wire[0..0]) & data_wire[21..21];
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l1_w6_n0_mux_dataout = sel_wire[0..0] & data_wire[14..14] # !(sel_wire[0..0]) & data_wire[6..6];
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l1_w6_n1_mux_dataout = sel_wire[0..0] & data_wire[30..30] # !(sel_wire[0..0]) & data_wire[22..22];
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l1_w7_n0_mux_dataout = sel_wire[0..0] & data_wire[15..15] # !(sel_wire[0..0]) & data_wire[7..7];
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l1_w7_n1_mux_dataout = sel_wire[0..0] & data_wire[31..31] # !(sel_wire[0..0]) & data_wire[23..23];
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l2_w0_n0_mux_dataout = sel_wire[3..3] & data_wire[33..33] # !(sel_wire[3..3]) & data_wire[32..32];
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l2_w1_n0_mux_dataout = sel_wire[3..3] & data_wire[35..35] # !(sel_wire[3..3]) & data_wire[34..34];
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l2_w2_n0_mux_dataout = sel_wire[3..3] & data_wire[37..37] # !(sel_wire[3..3]) & data_wire[36..36];
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l2_w3_n0_mux_dataout = sel_wire[3..3] & data_wire[39..39] # !(sel_wire[3..3]) & data_wire[38..38];
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l2_w4_n0_mux_dataout = sel_wire[3..3] & data_wire[41..41] # !(sel_wire[3..3]) & data_wire[40..40];
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l2_w5_n0_mux_dataout = sel_wire[3..3] & data_wire[43..43] # !(sel_wire[3..3]) & data_wire[42..42];
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l2_w6_n0_mux_dataout = sel_wire[3..3] & data_wire[45..45] # !(sel_wire[3..3]) & data_wire[44..44];
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l2_w7_n0_mux_dataout = sel_wire[3..3] & data_wire[47..47] # !(sel_wire[3..3]) & data_wire[46..46];
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data_wire[] = ( l1_w7_n1_mux_dataout, l1_w7_n0_mux_dataout, l1_w6_n1_mux_dataout, l1_w6_n0_mux_dataout, l1_w5_n1_mux_dataout, l1_w5_n0_mux_dataout, l1_w4_n1_mux_dataout, l1_w4_n0_mux_dataout, l1_w3_n1_mux_dataout, l1_w3_n0_mux_dataout, l1_w2_n1_mux_dataout, l1_w2_n0_mux_dataout, l1_w1_n1_mux_dataout, l1_w1_n0_mux_dataout, l1_w0_n1_mux_dataout, l1_w0_n0_mux_dataout, data[]);
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result[] = result_wire_ext[];
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result_wire_ext[] = ( l2_w7_n0_mux_dataout, l2_w6_n0_mux_dataout, l2_w5_n0_mux_dataout, l2_w4_n0_mux_dataout, l2_w3_n0_mux_dataout, l2_w2_n0_mux_dataout, l2_w1_n0_mux_dataout, l2_w0_n0_mux_dataout);
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sel_wire[] = ( sel[1..1], B"00", sel[0..0]);
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END;
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--VALID FILE
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