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81 lines
5.4 KiB
Plaintext
81 lines
5.4 KiB
Plaintext
--lpm_decode CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone V" LPM_DECODES=16 LPM_WIDTH=4 data enable eq
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--VERSION_BEGIN 22.1 cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC VERSION_END
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-- Copyright (C) 2022 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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--synthesis_resources = lut 18
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SUBDESIGN decode_tma
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(
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data[3..0] : input;
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enable : input;
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eq[15..0] : output;
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)
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VARIABLE
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data_wire[3..0] : WIRE;
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enable_wire : WIRE;
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eq_node[15..0] : WIRE;
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eq_wire[15..0] : WIRE;
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w_anode1073w[1..0] : WIRE;
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w_anode1082w[3..0] : WIRE;
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w_anode1099w[3..0] : WIRE;
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w_anode1109w[3..0] : WIRE;
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w_anode1119w[3..0] : WIRE;
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w_anode1129w[3..0] : WIRE;
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w_anode1139w[3..0] : WIRE;
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w_anode1149w[3..0] : WIRE;
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w_anode1159w[3..0] : WIRE;
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w_anode1171w[1..0] : WIRE;
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w_anode1178w[3..0] : WIRE;
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w_anode1189w[3..0] : WIRE;
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w_anode1199w[3..0] : WIRE;
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w_anode1209w[3..0] : WIRE;
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w_anode1219w[3..0] : WIRE;
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w_anode1229w[3..0] : WIRE;
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w_anode1239w[3..0] : WIRE;
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w_anode1249w[3..0] : WIRE;
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w_data1071w[2..0] : WIRE;
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BEGIN
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data_wire[] = data[];
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enable_wire = enable;
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eq[] = eq_node[];
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eq_node[15..0] = eq_wire[15..0];
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eq_wire[] = ( ( w_anode1249w[3..3], w_anode1239w[3..3], w_anode1229w[3..3], w_anode1219w[3..3], w_anode1209w[3..3], w_anode1199w[3..3], w_anode1189w[3..3], w_anode1178w[3..3]), ( w_anode1159w[3..3], w_anode1149w[3..3], w_anode1139w[3..3], w_anode1129w[3..3], w_anode1119w[3..3], w_anode1109w[3..3], w_anode1099w[3..3], w_anode1082w[3..3]));
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w_anode1073w[] = ( (w_anode1073w[0..0] & (! data_wire[3..3])), enable_wire);
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w_anode1082w[] = ( (w_anode1082w[2..2] & (! w_data1071w[2..2])), (w_anode1082w[1..1] & (! w_data1071w[1..1])), (w_anode1082w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]);
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w_anode1099w[] = ( (w_anode1099w[2..2] & (! w_data1071w[2..2])), (w_anode1099w[1..1] & (! w_data1071w[1..1])), (w_anode1099w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]);
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w_anode1109w[] = ( (w_anode1109w[2..2] & (! w_data1071w[2..2])), (w_anode1109w[1..1] & w_data1071w[1..1]), (w_anode1109w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]);
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w_anode1119w[] = ( (w_anode1119w[2..2] & (! w_data1071w[2..2])), (w_anode1119w[1..1] & w_data1071w[1..1]), (w_anode1119w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]);
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w_anode1129w[] = ( (w_anode1129w[2..2] & w_data1071w[2..2]), (w_anode1129w[1..1] & (! w_data1071w[1..1])), (w_anode1129w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]);
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w_anode1139w[] = ( (w_anode1139w[2..2] & w_data1071w[2..2]), (w_anode1139w[1..1] & (! w_data1071w[1..1])), (w_anode1139w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]);
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w_anode1149w[] = ( (w_anode1149w[2..2] & w_data1071w[2..2]), (w_anode1149w[1..1] & w_data1071w[1..1]), (w_anode1149w[0..0] & (! w_data1071w[0..0])), w_anode1073w[1..1]);
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w_anode1159w[] = ( (w_anode1159w[2..2] & w_data1071w[2..2]), (w_anode1159w[1..1] & w_data1071w[1..1]), (w_anode1159w[0..0] & w_data1071w[0..0]), w_anode1073w[1..1]);
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w_anode1171w[] = ( (w_anode1171w[0..0] & data_wire[3..3]), enable_wire);
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w_anode1178w[] = ( (w_anode1178w[2..2] & (! w_data1071w[2..2])), (w_anode1178w[1..1] & (! w_data1071w[1..1])), (w_anode1178w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]);
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w_anode1189w[] = ( (w_anode1189w[2..2] & (! w_data1071w[2..2])), (w_anode1189w[1..1] & (! w_data1071w[1..1])), (w_anode1189w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]);
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w_anode1199w[] = ( (w_anode1199w[2..2] & (! w_data1071w[2..2])), (w_anode1199w[1..1] & w_data1071w[1..1]), (w_anode1199w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]);
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w_anode1209w[] = ( (w_anode1209w[2..2] & (! w_data1071w[2..2])), (w_anode1209w[1..1] & w_data1071w[1..1]), (w_anode1209w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]);
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w_anode1219w[] = ( (w_anode1219w[2..2] & w_data1071w[2..2]), (w_anode1219w[1..1] & (! w_data1071w[1..1])), (w_anode1219w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]);
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w_anode1229w[] = ( (w_anode1229w[2..2] & w_data1071w[2..2]), (w_anode1229w[1..1] & (! w_data1071w[1..1])), (w_anode1229w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]);
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w_anode1239w[] = ( (w_anode1239w[2..2] & w_data1071w[2..2]), (w_anode1239w[1..1] & w_data1071w[1..1]), (w_anode1239w[0..0] & (! w_data1071w[0..0])), w_anode1171w[1..1]);
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w_anode1249w[] = ( (w_anode1249w[2..2] & w_data1071w[2..2]), (w_anode1249w[1..1] & w_data1071w[1..1]), (w_anode1249w[0..0] & w_data1071w[0..0]), w_anode1171w[1..1]);
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w_data1071w[2..0] = data_wire[2..0];
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END;
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--VALID FILE
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