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14917 lines
485 KiB
Plaintext
14917 lines
485 KiB
Plaintext
--altsyncram ACF_BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES="CARE" ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone V" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=524288 NUMWORDS_B=524288 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="OLD_DATA" WIDTH_A=8 WIDTH_B=8 WIDTHAD_A=19 WIDTHAD_B=19 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b rden_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 22.1 cbx_altera_syncram_nd_impl 2022:10:25:15:32:10:SC cbx_altsyncram 2022:10:25:15:32:10:SC cbx_cycloneii 2022:10:25:15:32:10:SC cbx_lpm_add_sub 2022:10:25:15:32:10:SC cbx_lpm_compare 2022:10:25:15:32:10:SC cbx_lpm_decode 2022:10:25:15:32:10:SC cbx_lpm_mux 2022:10:25:15:32:10:SC cbx_mgl 2022:10:25:15:42:35:SC cbx_nadder 2022:10:25:15:32:10:SC cbx_stratix 2022:10:25:15:32:10:SC cbx_stratixii 2022:10:25:15:32:10:SC cbx_stratixiii 2022:10:25:15:32:10:SC cbx_stratixv 2022:10:25:15:32:10:SC cbx_util_mgl 2022:10:25:15:32:10:SC VERSION_END
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-- Copyright (C) 2022 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and any partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details, at
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-- https://fpgasoftware.intel.com/eula.
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FUNCTION decode_2na (data[5..0], enable)
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RETURNS ( eq[63..0]);
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FUNCTION mux_ihb (data[511..0], sel[5..0])
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RETURNS ( result[7..0]);
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FUNCTION cyclonev_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
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WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, ENABLE_ECC, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init10, mem_init11, mem_init12, mem_init13, mem_init14, mem_init15, mem_init16, mem_init17, mem_init18, mem_init19, mem_init2, mem_init20, mem_init21, mem_init22, mem_init23, mem_init24, mem_init25, mem_init26, mem_init27, mem_init28, mem_init29, mem_init3, mem_init30, mem_init31, mem_init32, mem_init33, mem_init34, mem_init35, mem_init36, mem_init37, mem_init38, mem_init39, mem_init4, mem_init40, mem_init41, mem_init42, mem_init43, mem_init44, mem_init45, mem_init46, mem_init47, mem_init48, mem_init49, mem_init5, mem_init50, mem_init51, mem_init52, mem_init53, mem_init54, mem_init55, mem_init56, mem_init57, mem_init58, mem_init59, mem_init6, mem_init60, mem_init61, mem_init62, mem_init63, mem_init64, mem_init65, mem_init66, mem_init67, mem_init68, mem_init69, mem_init7, mem_init70, mem_init71, mem_init8, mem_init9, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, WIDTH_ECCSTATUS = 3)
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RETURNS ( dftout[8..0], eccstatus[WIDTH_ECCSTATUS-1..0], portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = lut 240 M10K 512 reg 6
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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SUBDESIGN altsyncram_qdq1
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(
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address_a[18..0] : input;
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address_b[18..0] : input;
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clock0 : input;
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data_a[7..0] : input;
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q_b[7..0] : output;
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rden_b : input;
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wren_a : input;
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)
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VARIABLE
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address_reg_b[5..0] : dffe;
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decode2 : decode_2na;
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mux3 : mux_ihb;
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ram_block1a0 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 0,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a1 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 1,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a2 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 2,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 2,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a3 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 3,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 3,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a4 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 4,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 4,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a5 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 5,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 5,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a6 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 6,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 6,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a7 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 0,
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PORT_A_FIRST_BIT_NUMBER = 7,
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PORT_A_LAST_ADDRESS = 8191,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 0,
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PORT_B_FIRST_BIT_NUMBER = 7,
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PORT_B_LAST_ADDRESS = 8191,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a8 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 8192,
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PORT_A_FIRST_BIT_NUMBER = 0,
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PORT_A_LAST_ADDRESS = 16383,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
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PORT_B_ADDRESS_WIDTH = 13,
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PORT_B_DATA_OUT_CLEAR = "none",
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PORT_B_DATA_WIDTH = 1,
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PORT_B_FIRST_ADDRESS = 8192,
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PORT_B_FIRST_BIT_NUMBER = 0,
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PORT_B_LAST_ADDRESS = 16383,
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
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PORT_B_LOGICAL_RAM_WIDTH = 8,
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PORT_B_READ_ENABLE_CLOCK = "clock0",
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RAM_BLOCK_TYPE = "AUTO"
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);
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ram_block1a9 : cyclonev_ram_block
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WITH (
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CLK0_CORE_CLOCK_ENABLE = "none",
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CLK0_INPUT_CLOCK_ENABLE = "none",
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CONNECTIVITY_CHECKING = "OFF",
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LOGICAL_RAM_NAME = "ALTSYNCRAM",
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MIXED_PORT_FEED_THROUGH_MODE = "old",
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OPERATION_MODE = "dual_port",
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PORT_A_ADDRESS_WIDTH = 13,
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PORT_A_DATA_WIDTH = 1,
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PORT_A_FIRST_ADDRESS = 8192,
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PORT_A_FIRST_BIT_NUMBER = 1,
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PORT_A_LAST_ADDRESS = 16383,
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PORT_A_LOGICAL_RAM_DEPTH = 524288,
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PORT_A_LOGICAL_RAM_WIDTH = 8,
|
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PORT_B_ADDRESS_CLEAR = "none",
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PORT_B_ADDRESS_CLOCK = "clock0",
|
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PORT_B_ADDRESS_WIDTH = 13,
|
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PORT_B_DATA_OUT_CLEAR = "none",
|
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PORT_B_DATA_WIDTH = 1,
|
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PORT_B_FIRST_ADDRESS = 8192,
|
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PORT_B_FIRST_BIT_NUMBER = 1,
|
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PORT_B_LAST_ADDRESS = 16383,
|
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PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
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PORT_B_LOGICAL_RAM_WIDTH = 8,
|
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PORT_B_READ_ENABLE_CLOCK = "clock0",
|
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RAM_BLOCK_TYPE = "AUTO"
|
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);
|
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ram_block1a10 : cyclonev_ram_block
|
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WITH (
|
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CLK0_CORE_CLOCK_ENABLE = "none",
|
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CLK0_INPUT_CLOCK_ENABLE = "none",
|
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CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
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MIXED_PORT_FEED_THROUGH_MODE = "old",
|
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OPERATION_MODE = "dual_port",
|
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PORT_A_ADDRESS_WIDTH = 13,
|
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PORT_A_DATA_WIDTH = 1,
|
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PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a11 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a12 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a13 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a14 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a15 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 8192,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 16383,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 8192,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 16383,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a16 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a17 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a18 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a19 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a20 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a21 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a22 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a23 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 16384,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 24575,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 16384,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 24575,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a24 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a25 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a26 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a27 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a28 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a29 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a30 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a31 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 24576,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 32767,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 24576,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 32767,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a32 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a33 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a34 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a35 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a36 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a37 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a38 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a39 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 32768,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 40959,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 32768,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 40959,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a40 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a41 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a42 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a43 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a44 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a45 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a46 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a47 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 40960,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 49151,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 40960,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 49151,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a48 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a49 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a50 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a51 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a52 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a53 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a54 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a55 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 49152,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 57343,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 49152,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 57343,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a56 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a57 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a58 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a59 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a60 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a61 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a62 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a63 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 57344,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 65535,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 57344,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 65535,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a64 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a65 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a66 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a67 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a68 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a69 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a70 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a71 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 65536,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 73727,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 65536,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 73727,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a72 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a73 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a74 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a75 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a76 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a77 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a78 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a79 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 73728,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 81919,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 73728,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 81919,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a80 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a81 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a82 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a83 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a84 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a85 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a86 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a87 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 81920,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 90111,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 81920,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 90111,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a88 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a89 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a90 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a91 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a92 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a93 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a94 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a95 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 90112,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 98303,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 90112,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 98303,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a96 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a97 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a98 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a99 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a100 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a101 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a102 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a103 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 98304,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 106495,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 98304,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 106495,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a104 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a105 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a106 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a107 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a108 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a109 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a110 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a111 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 106496,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 114687,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 106496,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 114687,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a112 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a113 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a114 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a115 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a116 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a117 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a118 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a119 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 114688,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 122879,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 114688,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 122879,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a120 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a121 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a122 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a123 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a124 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a125 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a126 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a127 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 122880,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 131071,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 122880,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 131071,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a128 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a129 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a130 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a131 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a132 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a133 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a134 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a135 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 131072,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 139263,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 131072,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 139263,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a136 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a137 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a138 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a139 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a140 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a141 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a142 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a143 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 139264,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 147455,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 139264,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 147455,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a144 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a145 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a146 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a147 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a148 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a149 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a150 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a151 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 147456,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 155647,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 147456,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 155647,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a152 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a153 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a154 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a155 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a156 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a157 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a158 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a159 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 155648,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 163839,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 155648,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 163839,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a160 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a161 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a162 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a163 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a164 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a165 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a166 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a167 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 163840,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 172031,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 163840,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 172031,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a168 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a169 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a170 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a171 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a172 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a173 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a174 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a175 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 172032,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 180223,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 172032,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 180223,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a176 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a177 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a178 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a179 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a180 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a181 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a182 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a183 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 180224,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 188415,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 180224,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 188415,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a184 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a185 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a186 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a187 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a188 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a189 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a190 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a191 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 188416,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 196607,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 188416,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 196607,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a192 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a193 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a194 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a195 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a196 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a197 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a198 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a199 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 196608,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 204799,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 196608,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 204799,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a200 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a201 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a202 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a203 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a204 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a205 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a206 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a207 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 204800,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 212991,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 204800,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 212991,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a208 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a209 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a210 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a211 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a212 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a213 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a214 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a215 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 212992,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 221183,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 212992,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 221183,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a216 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a217 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a218 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a219 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a220 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a221 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a222 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a223 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 221184,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 229375,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 221184,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 229375,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a224 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a225 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a226 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a227 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a228 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a229 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a230 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a231 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 229376,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 237567,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 229376,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 237567,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a232 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a233 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a234 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a235 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a236 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a237 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a238 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a239 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 237568,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 245759,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 237568,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 245759,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a240 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a241 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a242 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a243 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a244 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a245 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a246 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a247 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 245760,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 253951,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 245760,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 253951,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a248 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a249 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a250 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a251 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a252 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a253 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a254 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a255 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 253952,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 262143,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 253952,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 262143,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a256 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a257 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a258 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a259 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a260 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a261 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a262 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a263 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 262144,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 270335,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 262144,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 270335,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a264 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a265 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a266 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a267 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a268 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a269 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a270 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a271 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 270336,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 278527,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 270336,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 278527,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a272 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a273 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a274 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a275 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a276 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a277 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a278 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a279 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 278528,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 286719,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 278528,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 286719,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a280 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a281 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a282 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a283 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a284 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a285 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a286 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a287 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 286720,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 294911,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 286720,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 294911,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a288 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a289 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a290 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a291 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a292 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a293 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a294 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a295 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 294912,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 303103,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 294912,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 303103,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a296 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a297 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a298 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a299 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a300 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a301 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a302 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a303 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 303104,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 311295,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 303104,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 311295,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a304 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a305 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a306 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a307 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a308 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a309 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a310 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a311 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 311296,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 319487,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 311296,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 319487,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a312 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a313 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a314 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a315 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a316 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a317 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a318 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a319 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 319488,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 327679,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 319488,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 327679,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a320 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a321 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a322 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a323 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a324 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a325 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a326 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a327 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 327680,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 335871,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 327680,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 335871,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a328 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a329 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a330 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a331 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a332 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a333 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a334 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a335 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 335872,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 344063,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 335872,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 344063,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a336 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a337 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a338 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a339 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a340 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a341 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a342 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a343 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 344064,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 352255,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 344064,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 352255,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a344 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a345 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a346 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a347 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a348 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a349 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a350 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a351 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 352256,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 360447,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 352256,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 360447,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a352 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a353 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a354 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a355 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a356 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a357 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a358 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a359 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 360448,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 368639,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 360448,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 368639,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a360 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a361 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a362 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a363 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a364 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a365 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a366 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a367 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 368640,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 376831,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 368640,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 376831,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a368 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a369 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a370 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a371 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a372 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a373 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a374 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a375 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 376832,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 385023,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 376832,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 385023,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a376 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a377 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a378 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a379 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a380 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a381 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a382 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a383 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 385024,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 393215,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 385024,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 393215,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a384 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a385 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a386 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a387 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a388 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a389 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a390 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a391 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 393216,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 401407,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 393216,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 401407,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a392 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a393 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a394 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a395 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a396 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a397 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a398 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a399 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 401408,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 409599,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 401408,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 409599,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a400 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a401 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a402 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a403 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a404 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a405 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a406 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a407 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 409600,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 417791,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 409600,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 417791,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a408 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a409 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a410 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a411 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a412 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a413 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a414 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a415 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 417792,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 425983,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 417792,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 425983,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a416 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a417 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a418 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a419 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a420 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a421 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a422 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a423 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 425984,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 434175,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 425984,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 434175,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a424 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a425 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a426 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a427 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a428 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a429 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a430 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a431 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 434176,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 442367,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 434176,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 442367,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a432 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a433 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a434 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a435 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a436 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a437 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a438 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a439 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 442368,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 450559,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 442368,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 450559,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a440 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a441 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a442 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a443 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a444 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a445 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a446 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a447 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 450560,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 458751,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 450560,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 458751,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a448 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a449 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a450 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a451 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a452 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a453 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a454 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a455 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 458752,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 466943,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 458752,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 466943,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a456 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a457 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a458 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a459 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a460 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a461 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a462 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a463 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 466944,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 475135,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 466944,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 475135,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a464 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a465 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a466 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a467 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a468 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a469 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a470 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a471 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 475136,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 483327,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 475136,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 483327,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a472 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a473 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a474 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a475 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a476 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a477 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a478 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a479 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 483328,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 491519,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 483328,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 491519,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a480 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a481 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a482 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a483 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a484 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a485 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a486 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a487 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 491520,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 499711,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 491520,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 499711,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a488 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a489 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a490 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a491 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a492 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a493 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a494 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a495 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 499712,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 507903,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 499712,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 507903,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a496 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a497 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a498 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a499 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a500 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a501 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a502 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a503 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 507904,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 516095,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 507904,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 516095,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a504 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 0,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 0,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a505 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 1,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 1,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a506 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 2,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 2,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a507 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 3,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 3,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a508 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 4,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 4,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a509 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 5,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 5,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a510 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 6,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 6,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
ram_block1a511 : cyclonev_ram_block
|
|
WITH (
|
|
CLK0_CORE_CLOCK_ENABLE = "none",
|
|
CLK0_INPUT_CLOCK_ENABLE = "none",
|
|
CONNECTIVITY_CHECKING = "OFF",
|
|
LOGICAL_RAM_NAME = "ALTSYNCRAM",
|
|
MIXED_PORT_FEED_THROUGH_MODE = "old",
|
|
OPERATION_MODE = "dual_port",
|
|
PORT_A_ADDRESS_WIDTH = 13,
|
|
PORT_A_DATA_WIDTH = 1,
|
|
PORT_A_FIRST_ADDRESS = 516096,
|
|
PORT_A_FIRST_BIT_NUMBER = 7,
|
|
PORT_A_LAST_ADDRESS = 524287,
|
|
PORT_A_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_A_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_ADDRESS_CLEAR = "none",
|
|
PORT_B_ADDRESS_CLOCK = "clock0",
|
|
PORT_B_ADDRESS_WIDTH = 13,
|
|
PORT_B_DATA_OUT_CLEAR = "none",
|
|
PORT_B_DATA_WIDTH = 1,
|
|
PORT_B_FIRST_ADDRESS = 516096,
|
|
PORT_B_FIRST_BIT_NUMBER = 7,
|
|
PORT_B_LAST_ADDRESS = 524287,
|
|
PORT_B_LOGICAL_RAM_DEPTH = 524288,
|
|
PORT_B_LOGICAL_RAM_WIDTH = 8,
|
|
PORT_B_READ_ENABLE_CLOCK = "clock0",
|
|
RAM_BLOCK_TYPE = "AUTO"
|
|
);
|
|
address_a_wire[18..0] : WIRE;
|
|
address_b_sel[5..0] : WIRE;
|
|
address_b_wire[18..0] : WIRE;
|
|
|
|
BEGIN
|
|
address_reg_b[].clk = clock0;
|
|
address_reg_b[].d = address_b_sel[];
|
|
address_reg_b[].ena = rden_b;
|
|
decode2.data[5..0] = address_a_wire[18..13];
|
|
decode2.enable = wren_a;
|
|
mux3.data[] = ( ram_block1a[511..0].portbdataout[0..0]);
|
|
mux3.sel[] = address_reg_b[].q;
|
|
ram_block1a[511..0].clk0 = clock0;
|
|
ram_block1a[511..0].portaaddr[] = ( address_a_wire[12..0]);
|
|
ram_block1a[0].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[1].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[2].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[3].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[4].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[5].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[6].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[7].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[8].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[9].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[10].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[11].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[12].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[13].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[14].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[15].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[16].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[17].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[18].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[19].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[20].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[21].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[22].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[23].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[24].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[25].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[26].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[27].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[28].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[29].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[30].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[31].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[32].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[33].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[34].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[35].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[36].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[37].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[38].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[39].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[40].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[41].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[42].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[43].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[44].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[45].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[46].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[47].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[48].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[49].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[50].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[51].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[52].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[53].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[54].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[55].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[56].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[57].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[58].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[59].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[60].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[61].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[62].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[63].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[64].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[65].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[66].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[67].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[68].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[69].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[70].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[71].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[72].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[73].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[74].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[75].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[76].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[77].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[78].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[79].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[80].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[81].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[82].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[83].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[84].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[85].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[86].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[87].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[88].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[89].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[90].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[91].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[92].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[93].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[94].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[95].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[96].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[97].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[98].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[99].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[100].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[101].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[102].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[103].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[104].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[105].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[106].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[107].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[108].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[109].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[110].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[111].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[112].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[113].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[114].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[115].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[116].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[117].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[118].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[119].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[120].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[121].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[122].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[123].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[124].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[125].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[126].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[127].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[128].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[129].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[130].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[131].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[132].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[133].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[134].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[135].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[136].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[137].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[138].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[139].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[140].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[141].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[142].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[143].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[144].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[145].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[146].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[147].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[148].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[149].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[150].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[151].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[152].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[153].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[154].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[155].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[156].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[157].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[158].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[159].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[160].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[161].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[162].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[163].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[164].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[165].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[166].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[167].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[168].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[169].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[170].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[171].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[172].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[173].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[174].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[175].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[176].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[177].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[178].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[179].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[180].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[181].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[182].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[183].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[184].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[185].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[186].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[187].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[188].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[189].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[190].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[191].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[192].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[193].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[194].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[195].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[196].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[197].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[198].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[199].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[200].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[201].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[202].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[203].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[204].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[205].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[206].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[207].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[208].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[209].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[210].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[211].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[212].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[213].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[214].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[215].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[216].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[217].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[218].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[219].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[220].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[221].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[222].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[223].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[224].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[225].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[226].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[227].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[228].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[229].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[230].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[231].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[232].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[233].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[234].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[235].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[236].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[237].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[238].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[239].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[240].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[241].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[242].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[243].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[244].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[245].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[246].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[247].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[248].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[249].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[250].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[251].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[252].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[253].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[254].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[255].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[256].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[257].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[258].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[259].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[260].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[261].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[262].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[263].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[264].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[265].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[266].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[267].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[268].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[269].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[270].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[271].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[272].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[273].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[274].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[275].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[276].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[277].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[278].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[279].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[280].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[281].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[282].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[283].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[284].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[285].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[286].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[287].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[288].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[289].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[290].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[291].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[292].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[293].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[294].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[295].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[296].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[297].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[298].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[299].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[300].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[301].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[302].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[303].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[304].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[305].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[306].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[307].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[308].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[309].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[310].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[311].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[312].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[313].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[314].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[315].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[316].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[317].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[318].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[319].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[320].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[321].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[322].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[323].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[324].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[325].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[326].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[327].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[328].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[329].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[330].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[331].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[332].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[333].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[334].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[335].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[336].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[337].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[338].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[339].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[340].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[341].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[342].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[343].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[344].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[345].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[346].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[347].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[348].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[349].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[350].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[351].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[352].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[353].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[354].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[355].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[356].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[357].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[358].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[359].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[360].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[361].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[362].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[363].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[364].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[365].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[366].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[367].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[368].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[369].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[370].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[371].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[372].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[373].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[374].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[375].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[376].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[377].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[378].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[379].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[380].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[381].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[382].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[383].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[384].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[385].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[386].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[387].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[388].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[389].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[390].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[391].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[392].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[393].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[394].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[395].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[396].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[397].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[398].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[399].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[400].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[401].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[402].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[403].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[404].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[405].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[406].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[407].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[408].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[409].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[410].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[411].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[412].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[413].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[414].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[415].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[416].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[417].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[418].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[419].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[420].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[421].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[422].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[423].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[424].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[425].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[426].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[427].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[428].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[429].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[430].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[431].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[432].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[433].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[434].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[435].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[436].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[437].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[438].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[439].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[440].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[441].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[442].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[443].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[444].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[445].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[446].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[447].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[448].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[449].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[450].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[451].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[452].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[453].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[454].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[455].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[456].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[457].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[458].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[459].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[460].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[461].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[462].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[463].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[464].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[465].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[466].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[467].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[468].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[469].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[470].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[471].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[472].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[473].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[474].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[475].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[476].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[477].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[478].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[479].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[480].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[481].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[482].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[483].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[484].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[485].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[486].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[487].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[488].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[489].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[490].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[491].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[492].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[493].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[494].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[495].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[496].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[497].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[498].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[499].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[500].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[501].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[502].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[503].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[504].portadatain[] = ( data_a[0..0]);
|
|
ram_block1a[505].portadatain[] = ( data_a[1..1]);
|
|
ram_block1a[506].portadatain[] = ( data_a[2..2]);
|
|
ram_block1a[507].portadatain[] = ( data_a[3..3]);
|
|
ram_block1a[508].portadatain[] = ( data_a[4..4]);
|
|
ram_block1a[509].portadatain[] = ( data_a[5..5]);
|
|
ram_block1a[510].portadatain[] = ( data_a[6..6]);
|
|
ram_block1a[511].portadatain[] = ( data_a[7..7]);
|
|
ram_block1a[511..0].portawe = ( decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..63], decode2.eq[63..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..62], decode2.eq[62..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..61], decode2.eq[61..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..60], decode2.eq[60..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..59], decode2.eq[59..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..58], decode2.eq[58..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..57], decode2.eq[57..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..56], decode2.eq[56..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..55], decode2.eq[55..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..54], decode2.eq[54..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..53], decode2.eq[53..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..52], decode2.eq[52..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..51], decode2.eq[51..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..50], decode2.eq[50..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..49], decode2.eq[49..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..48], decode2.eq[48..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..47], decode2.eq[47..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..46], decode2.eq[46..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..45], decode2.eq[45..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..44], decode2.eq[44..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..43], decode2.eq[43..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..42], decode2.eq[42..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..41], decode2.eq[41..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..40], decode2.eq[40..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..39], decode2.eq[39..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..38], decode2.eq[38..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..37], decode2.eq[37..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..36], decode2.eq[36..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..35], decode2.eq[35..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..34], decode2.eq[34..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..33], decode2.eq[33..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..32], decode2.eq[32..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..31], decode2.eq[31..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..30], decode2.eq[30..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..29], decode2.eq[29..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..28], decode2.eq[28..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..27], decode2.eq[27..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..26], decode2.eq[26..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..25], decode2.eq[25..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..24], decode2.eq[24..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..23], decode2.eq[23..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..22], decode2.eq[22..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..21], decode2.eq[21..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..20], decode2.eq[20..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..19], decode2.eq[19..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..18], decode2.eq[18..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..17], decode2.eq[17..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..16], decode2.eq[16..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..15], decode2.eq[15..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..14], decode2.eq[14..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..13], decode2.eq[13..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..12], decode2.eq[12..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..11], decode2.eq[11..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..10], decode2.eq[10..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..9], decode2.eq[9..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..8], decode2.eq[8..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..7], decode2.eq[7..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..6], decode2.eq[6..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..5], decode2.eq[5..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..4], decode2.eq[4..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..3], decode2.eq[3..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..2], decode2.eq[2..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..1], decode2.eq[1..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0], decode2.eq[0..0]);
|
|
ram_block1a[511..0].portbaddr[] = ( address_b_wire[12..0]);
|
|
ram_block1a[511..0].portbre = rden_b;
|
|
address_a_wire[] = address_a[];
|
|
address_b_sel[5..0] = address_b[18..13];
|
|
address_b_wire[] = address_b[];
|
|
q_b[] = mux3.result[];
|
|
END;
|
|
--VALID FILE
|