798 lines
32 KiB
C
798 lines
32 KiB
C
// #################################################################################################
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// # << NEORV32: neorv32_rte.c - NEORV32 Runtime Environment >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file neorv32_rte.c
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* @brief NEORV32 Runtime Environment.
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**************************************************************************/
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#include "neorv32.h"
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#include "neorv32_rte.h"
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/**********************************************************************//**
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* The >private< trap vector look-up table of the NEORV32 RTE.
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**************************************************************************/
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static uint32_t __neorv32_rte_vector_lut[NEORV32_RTE_NUM_TRAPS] __attribute__((unused)); // trap handler vector table
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// private functions
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static void __attribute__((__interrupt__)) __neorv32_rte_core(void) __attribute__((aligned(4)));
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static void __neorv32_rte_debug_handler(void);
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static void __neorv32_rte_print_true_false(int state);
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static void __neorv32_rte_print_checkbox(int state);
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static void __neorv32_rte_print_hex_word(uint32_t num);
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static void __neorv32_rte_print_hex_half(uint16_t num);
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/**********************************************************************//**
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* Setup NEORV32 runtime environment.
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*
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* @note This function installs a debug handler for ALL trap sources, which
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* gives detailed information about the trap. Actual handler can be installed afterwards
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* via neorv32_rte_handler_install(uint8_t id, void (*handler)(void)).
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**************************************************************************/
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void neorv32_rte_setup(void) {
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// configure trap handler base address
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neorv32_cpu_csr_write(CSR_MTVEC, (uint32_t)(&__neorv32_rte_core));
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// disable all IRQ channels
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neorv32_cpu_csr_write(CSR_MIE, 0);
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// clear all pending IRQs
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neorv32_cpu_csr_write(CSR_MIP, 0);
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// clear BUSKEEPER error flags
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NEORV32_BUSKEEPER.CTRL = 0;
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// install debug handler for all trap sources
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uint8_t id;
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for (id = 0; id < (sizeof(__neorv32_rte_vector_lut)/sizeof(__neorv32_rte_vector_lut[0])); id++) {
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neorv32_rte_handler_uninstall(id); // this will configure the debug handler
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}
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}
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/**********************************************************************//**
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* Install trap handler function to NEORV32 runtime environment.
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*
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* @param[in] id Identifier (type) of the targeted trap. See #NEORV32_RTE_TRAP_enum.
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* @param[in] handler The actual handler function for the specified trap (function MUST be of type "void function(void);").
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* @return 0 if success, 1 if error (invalid id or targeted trap not supported).
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**************************************************************************/
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int neorv32_rte_handler_install(uint8_t id, void (*handler)(void)) {
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// id valid?
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if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)handler; // install handler
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return 0;
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}
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return 1;
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}
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/**********************************************************************//**
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* Uninstall trap handler function from NEORV32 runtime environment, which was
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* previously installed via neorv32_rte_handler_install(uint8_t id, void (*handler)(void)).
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*
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* @param[in] id Identifier (type) of the targeted trap. See #NEORV32_RTE_TRAP_enum.
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* @return 0 if success, 1 if error (invalid id or targeted trap not supported).
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**************************************************************************/
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int neorv32_rte_handler_uninstall(uint8_t id) {
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// id valid?
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if ((id >= RTE_TRAP_I_MISALIGNED) && (id <= CSR_MIE_FIRQ15E)) {
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__neorv32_rte_vector_lut[id] = (uint32_t)(&__neorv32_rte_debug_handler); // use dummy handler in case the trap is accidentally triggered
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return 0;
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}
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return 1;
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}
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/**********************************************************************//**
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* This is the [private!] core of the NEORV32 RTE.
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*
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* @warning When using the the RTE, this function is the ONLY function that uses the 'interrupt' attribute!
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**************************************************************************/
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static void __attribute__((__interrupt__)) __attribute__((aligned(4))) __neorv32_rte_core(void) {
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uint32_t rte_mcause = neorv32_cpu_csr_read(CSR_MCAUSE);
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// find according trap handler
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uint32_t rte_handler;
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switch (rte_mcause) {
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case TRAP_CODE_I_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_MISALIGNED]; break;
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case TRAP_CODE_I_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ACCESS]; break;
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case TRAP_CODE_I_ILLEGAL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_I_ILLEGAL]; break;
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case TRAP_CODE_BREAKPOINT: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_BREAKPOINT]; break;
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case TRAP_CODE_L_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_MISALIGNED]; break;
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case TRAP_CODE_L_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_L_ACCESS]; break;
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case TRAP_CODE_S_MISALIGNED: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_MISALIGNED]; break;
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case TRAP_CODE_S_ACCESS: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_S_ACCESS]; break;
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case TRAP_CODE_UENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_UENV_CALL]; break;
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case TRAP_CODE_MENV_CALL: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MENV_CALL]; break;
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case TRAP_CODE_MSI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MSI]; break;
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case TRAP_CODE_MTI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MTI]; break;
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case TRAP_CODE_MEI: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_MEI]; break;
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case TRAP_CODE_FIRQ_0: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_0]; break;
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case TRAP_CODE_FIRQ_1: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_1]; break;
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case TRAP_CODE_FIRQ_2: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_2]; break;
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case TRAP_CODE_FIRQ_3: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_3]; break;
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case TRAP_CODE_FIRQ_4: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_4]; break;
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case TRAP_CODE_FIRQ_5: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_5]; break;
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case TRAP_CODE_FIRQ_6: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_6]; break;
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case TRAP_CODE_FIRQ_7: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_7]; break;
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case TRAP_CODE_FIRQ_8: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_8]; break;
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case TRAP_CODE_FIRQ_9: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_9]; break;
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case TRAP_CODE_FIRQ_10: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_10]; break;
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case TRAP_CODE_FIRQ_11: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_11]; break;
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case TRAP_CODE_FIRQ_12: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_12]; break;
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case TRAP_CODE_FIRQ_13: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_13]; break;
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case TRAP_CODE_FIRQ_14: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_14]; break;
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case TRAP_CODE_FIRQ_15: rte_handler = __neorv32_rte_vector_lut[RTE_TRAP_FIRQ_15]; break;
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default: rte_handler = (uint32_t)(&__neorv32_rte_debug_handler); break;
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}
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// execute handler
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void (*handler_pnt)(void);
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handler_pnt = (void*)rte_handler;
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(*handler_pnt)();
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// compute return address
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// WARNING: some traps might NOT be resumable! (e.g. instruction access fault)
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if (((int32_t)rte_mcause) >= 0) { // modify pc only if not interrupt (MSB cleared)
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uint32_t rte_mepc = neorv32_cpu_csr_read(CSR_MEPC);
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// get low half word of faulting instruction
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uint32_t rte_trap_inst = (uint32_t)neorv32_cpu_load_unsigned_half(rte_mepc);
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rte_mepc += 4; // default: faulting instruction is uncompressed
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if (neorv32_cpu_csr_read(CSR_MISA) & (1 << CSR_MISA_C)) { // C extension implemented?
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if ((rte_trap_inst & 3) != 3) { // faulting instruction is compressed instruction
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rte_mepc -= 2;
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}
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}
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// store new return address
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neorv32_cpu_csr_write(CSR_MEPC, rte_mepc);
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}
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Debug trap handler, printing various information via UART.
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* @note This function is used by neorv32_rte_handler_uninstall(void) only.
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**************************************************************************/
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static void __neorv32_rte_debug_handler(void) {
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if (neorv32_uart0_available() == 0) {
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return; // handler cannot output anything if UART0 is not implemented
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}
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// intro
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neorv32_uart0_puts("<RTE> ");
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// cause
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uint32_t trap_cause = neorv32_cpu_csr_read(CSR_MCAUSE);
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switch (trap_cause) {
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case TRAP_CODE_I_MISALIGNED: neorv32_uart0_puts("Instruction address misaligned"); break;
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case TRAP_CODE_I_ACCESS: neorv32_uart0_puts("Instruction access fault"); break;
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case TRAP_CODE_I_ILLEGAL: neorv32_uart0_puts("Illegal instruction"); break;
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case TRAP_CODE_BREAKPOINT: neorv32_uart0_puts("Breakpoint"); break;
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case TRAP_CODE_L_MISALIGNED: neorv32_uart0_puts("Load address misaligned"); break;
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case TRAP_CODE_L_ACCESS: neorv32_uart0_puts("Load access fault"); break;
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case TRAP_CODE_S_MISALIGNED: neorv32_uart0_puts("Store address misaligned"); break;
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case TRAP_CODE_S_ACCESS: neorv32_uart0_puts("Store access fault"); break;
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case TRAP_CODE_UENV_CALL: neorv32_uart0_puts("Environment call from U-mode"); break;
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case TRAP_CODE_MENV_CALL: neorv32_uart0_puts("Environment call from M-mode"); break;
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case TRAP_CODE_MSI: neorv32_uart0_puts("Machine software IRQ"); break;
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case TRAP_CODE_MTI: neorv32_uart0_puts("Machine timer IRQ"); break;
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case TRAP_CODE_MEI: neorv32_uart0_puts("Machine external IRQ"); break;
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case TRAP_CODE_FIRQ_0:
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case TRAP_CODE_FIRQ_1:
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case TRAP_CODE_FIRQ_2:
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case TRAP_CODE_FIRQ_3:
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case TRAP_CODE_FIRQ_4:
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case TRAP_CODE_FIRQ_5:
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case TRAP_CODE_FIRQ_6:
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case TRAP_CODE_FIRQ_7:
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case TRAP_CODE_FIRQ_8:
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case TRAP_CODE_FIRQ_9:
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case TRAP_CODE_FIRQ_10:
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case TRAP_CODE_FIRQ_11:
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case TRAP_CODE_FIRQ_12:
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case TRAP_CODE_FIRQ_13:
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case TRAP_CODE_FIRQ_14:
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case TRAP_CODE_FIRQ_15: neorv32_uart0_puts("Fast IRQ "); __neorv32_rte_print_hex_word(trap_cause & 0xf); break;
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default: neorv32_uart0_puts("Unknown trap cause: "); __neorv32_rte_print_hex_word(trap_cause); break;
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}
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// check cause if bus access fault exception
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if ((trap_cause == TRAP_CODE_I_ACCESS) || (trap_cause == TRAP_CODE_L_ACCESS) || (trap_cause == TRAP_CODE_S_ACCESS)) {
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uint32_t bus_err = NEORV32_BUSKEEPER.CTRL;
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if (bus_err & (1<<BUSKEEPER_ERR_FLAG)) { // exception caused by bus system?
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if (bus_err & (1<<BUSKEEPER_ERR_TYPE)) {
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neorv32_uart0_puts(" [TIMEOUT_ERR]");
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}
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else {
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neorv32_uart0_puts(" [DEVICE_ERR]");
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}
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}
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else { // exception was not caused by bus system -> has to be caused by PMP rule violation
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neorv32_uart0_puts(" [PMP_ERR]");
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}
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}
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// instruction address
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neorv32_uart0_puts(" @ PC=");
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uint32_t mepc = neorv32_cpu_csr_read(CSR_MEPC);
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__neorv32_rte_print_hex_word(mepc);
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// additional info
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if (trap_cause == TRAP_CODE_I_ILLEGAL) { // illegal instruction
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neorv32_uart0_puts(", INST=");
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uint32_t instr_lo = (uint32_t)neorv32_cpu_load_unsigned_half(mepc);
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uint32_t instr_hi = (uint32_t)neorv32_cpu_load_unsigned_half(mepc + 2);
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if ((instr_lo & 3) != 3) { // is compressed instruction
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__neorv32_rte_print_hex_half(instr_lo);
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}
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else {
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__neorv32_rte_print_hex_word(((uint32_t)instr_hi << 16) | (uint32_t)instr_lo);
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}
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}
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else if ((trap_cause & 0x80000000U) == 0) { // not an interrupt
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neorv32_uart0_puts(", ADDR=");
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__neorv32_rte_print_hex_word(neorv32_cpu_csr_read(CSR_MTVAL));
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}
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// outro
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neorv32_uart0_puts(" </RTE>\n");
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}
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/**********************************************************************//**
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* NEORV32 runtime environment: Print hardware configuration information via UART
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**************************************************************************/
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void neorv32_rte_print_hw_config(void) {
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if (neorv32_uart0_available() == 0) {
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return; // cannot output anything if UART0 is not implemented
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}
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uint32_t tmp;
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int i;
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char c;
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neorv32_uart0_printf("\n\n<< NEORV32 Processor Configuration >>\n");
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// CPU configuration
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neorv32_uart0_printf("\n====== Core ======\n");
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// general
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neorv32_uart0_printf("Is simulation: "); __neorv32_rte_print_true_false(neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_IS_SIM));
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neorv32_uart0_printf("Clock speed: %u Hz\n", NEORV32_SYSINFO.CLK);
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neorv32_uart0_printf("On-chip debugger: "); __neorv32_rte_print_true_false(NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_OCD));
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// IDs
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neorv32_uart0_printf("Custom ID: 0x%x\n"
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"Hart ID: 0x%x\n"
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"Vendor ID: 0x%x\n"
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"Architecture ID: 0x%x\n"
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"Implementation ID: 0x%x",
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NEORV32_SYSINFO.CUSTOM_ID,
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neorv32_cpu_csr_read(CSR_MHARTID),
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neorv32_cpu_csr_read(CSR_MVENDORID),
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neorv32_cpu_csr_read(CSR_MARCHID),
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neorv32_cpu_csr_read(CSR_MIMPID));
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neorv32_uart0_printf(" (v");
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neorv32_rte_print_hw_version();
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neorv32_uart0_printf(")\n");
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// CPU architecture and endianness
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neorv32_uart0_printf("Architecture: ");
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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tmp = (tmp >> 30) & 0x03;
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if (tmp == 1) {
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neorv32_uart0_printf("rv32-little");
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}
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else {
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neorv32_uart0_printf("unknown");
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}
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// CPU extensions
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neorv32_uart0_printf("\nISA extensions: ");
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tmp = neorv32_cpu_csr_read(CSR_MISA);
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for (i=0; i<26; i++) {
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if (tmp & (1 << i)) {
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c = (char)('A' + i);
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neorv32_uart0_putc(c);
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neorv32_uart0_putc(' ');
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}
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}
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// Z* CPU extensions
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tmp = neorv32_cpu_csr_read(CSR_MXISA);
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if (tmp & (1<<CSR_MXISA_ZICSR)) {
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neorv32_uart0_printf("Zicsr ");
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}
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if (tmp & (1<<CSR_MXISA_ZICNTR)) {
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neorv32_uart0_printf("Zicntr ");
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}
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if (tmp & (1<<CSR_MXISA_ZIHPM)) {
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neorv32_uart0_printf("Zihpm ");
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}
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if (tmp & (1<<CSR_MXISA_ZIFENCEI)) {
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neorv32_uart0_printf("Zifencei ");
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}
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if (tmp & (1<<CSR_MXISA_ZMMUL)) {
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neorv32_uart0_printf("Zmmul ");
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}
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if (tmp & (1<<CSR_MXISA_ZFINX)) {
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neorv32_uart0_printf("Zfinx ");
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}
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if (tmp & (1<<CSR_MXISA_ZXCFU)) {
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neorv32_uart0_printf("Zxcfu ");
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}
|
|
if (tmp & (1<<CSR_MXISA_SDEXT)) {
|
|
neorv32_uart0_printf("Sdext ");
|
|
}
|
|
if (tmp & (1<<CSR_MXISA_SDTRIG)) {
|
|
neorv32_uart0_printf("Sdtrig ");
|
|
}
|
|
|
|
// CPU tuning options
|
|
neorv32_uart0_printf("\nTuning options: ");
|
|
if (tmp & (1<<CSR_MXISA_FASTMUL)) {
|
|
neorv32_uart0_printf("FAST_MUL ");
|
|
}
|
|
if (tmp & (1<<CSR_MXISA_FASTSHIFT)) {
|
|
neorv32_uart0_printf("FAST_SHIFT ");
|
|
}
|
|
|
|
// check physical memory protection
|
|
neorv32_uart0_printf("\nPhys. Mem. Prot.: ");
|
|
uint32_t pmp_num_regions = neorv32_cpu_pmp_get_num_regions();
|
|
if (pmp_num_regions != 0) {
|
|
neorv32_uart0_printf("%u region(s), %u bytes minimal granularity, OFF/TOR mode only", pmp_num_regions, neorv32_cpu_pmp_get_granularity());
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("not implemented");
|
|
}
|
|
|
|
// check hardware performance monitors
|
|
neorv32_uart0_printf("\nHPM Counters: ");
|
|
uint32_t hpm_num = neorv32_cpu_hpm_get_num_counters();
|
|
if (hpm_num != 0) {
|
|
neorv32_uart0_printf("%u counter(s), %u bit(s) wide", hpm_num, neorv32_cpu_hpm_get_size());
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("not implemented");
|
|
}
|
|
|
|
|
|
// Memory configuration
|
|
neorv32_uart0_printf("\n\n====== Memory ======\n");
|
|
|
|
neorv32_uart0_printf("Boot configuration: Boot ");
|
|
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_BOOTLOADER)) {
|
|
neorv32_uart0_printf("via Bootloader\n");
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("from memory (@ 0x%x)\n", NEORV32_SYSINFO.ISPACE_BASE);
|
|
}
|
|
|
|
neorv32_uart0_printf("Instr. base address: 0x%x\n", NEORV32_SYSINFO.ISPACE_BASE);
|
|
|
|
// IMEM
|
|
neorv32_uart0_printf("Internal IMEM: ");
|
|
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_INT_IMEM)) {
|
|
neorv32_uart0_printf("yes, %u bytes\n", NEORV32_SYSINFO.IMEM_SIZE);
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("no\n");
|
|
}
|
|
|
|
// DMEM
|
|
neorv32_uart0_printf("Data base address: 0x%x\n", NEORV32_SYSINFO.DSPACE_BASE);
|
|
neorv32_uart0_printf("Internal DMEM: ");
|
|
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_INT_DMEM)) {
|
|
neorv32_uart0_printf("yes, %u bytes\n", NEORV32_SYSINFO.DMEM_SIZE);
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("no\n");
|
|
}
|
|
|
|
// i-cache
|
|
neorv32_uart0_printf("Internal i-cache: ");
|
|
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_ICACHE)) {
|
|
neorv32_uart0_printf("yes, ");
|
|
|
|
uint32_t ic_block_size = (NEORV32_SYSINFO.CACHE >> SYSINFO_CACHE_IC_BLOCK_SIZE_0) & 0x0F;
|
|
if (ic_block_size) {
|
|
ic_block_size = 1 << ic_block_size;
|
|
}
|
|
else {
|
|
ic_block_size = 0;
|
|
}
|
|
|
|
uint32_t ic_num_blocks = (NEORV32_SYSINFO.CACHE >> SYSINFO_CACHE_IC_NUM_BLOCKS_0) & 0x0F;
|
|
if (ic_num_blocks) {
|
|
ic_num_blocks = 1 << ic_num_blocks;
|
|
}
|
|
else {
|
|
ic_num_blocks = 0;
|
|
}
|
|
|
|
uint32_t ic_associativity = (NEORV32_SYSINFO.CACHE >> SYSINFO_CACHE_IC_ASSOCIATIVITY_0) & 0x0F;
|
|
ic_associativity = 1 << ic_associativity;
|
|
|
|
neorv32_uart0_printf("%u bytes, %u set(s), %u block(s) per set, %u bytes per block", ic_associativity*ic_num_blocks*ic_block_size, ic_associativity, ic_num_blocks, ic_block_size);
|
|
if (ic_associativity == 1) {
|
|
neorv32_uart0_printf(" (direct-mapped)\n");
|
|
}
|
|
else if (((NEORV32_SYSINFO.CACHE >> SYSINFO_CACHE_IC_REPLACEMENT_0) & 0x0F) == 1) {
|
|
neorv32_uart0_printf(" (LRU replacement policy)\n");
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("\n");
|
|
}
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("no\n");
|
|
}
|
|
|
|
neorv32_uart0_printf("Ext. bus interface: ");
|
|
__neorv32_rte_print_true_false(NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_EXT));
|
|
neorv32_uart0_printf("Ext. bus endianness: ");
|
|
if (NEORV32_SYSINFO.SOC & (1 << SYSINFO_SOC_MEM_EXT_ENDIAN)) {
|
|
neorv32_uart0_printf("big\n");
|
|
}
|
|
else {
|
|
neorv32_uart0_printf("little\n");
|
|
}
|
|
|
|
// peripherals
|
|
neorv32_uart0_printf("\n====== Peripherals ======\n");
|
|
|
|
tmp = NEORV32_SYSINFO.SOC;
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_GPIO)); neorv32_uart0_printf(" GPIO\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_MTIME)); neorv32_uart0_printf(" MTIME\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_UART0)); neorv32_uart0_printf(" UART0\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_UART1)); neorv32_uart0_printf(" UART1\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_SPI)); neorv32_uart0_printf(" SPI\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_TWI)); neorv32_uart0_printf(" TWI\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_PWM)); neorv32_uart0_printf(" PWM\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_WDT)); neorv32_uart0_printf(" WDT\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_TRNG)); neorv32_uart0_printf(" TRNG\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_CFS)); neorv32_uart0_printf(" CFS\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_SLINK)); neorv32_uart0_printf(" SLINK\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_NEOLED)); neorv32_uart0_printf(" NEOLED\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_XIRQ)); neorv32_uart0_printf(" XIRQ\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_GPTMR)); neorv32_uart0_printf(" GPTMR\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_XIP)); neorv32_uart0_printf(" XIP\n");
|
|
__neorv32_rte_print_checkbox(tmp & (1 << SYSINFO_SOC_IO_ONEWIRE)); neorv32_uart0_printf(" ONEWIRE\n");
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Private function to print yes or no.
|
|
* @note This function is used by neorv32_rte_print_hw_config(void) only.
|
|
*
|
|
* @param[in] state Print 'yes' when !=0, print 'no' when 0
|
|
**************************************************************************/
|
|
static void __neorv32_rte_print_true_false(int state) {
|
|
|
|
if (state) {
|
|
neorv32_uart0_puts("yes\n");
|
|
}
|
|
else {
|
|
neorv32_uart0_puts("no\n");
|
|
}
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Private function to print [x] or [ ].
|
|
* @note This function is used by neorv32_rte_print_hw_config(void) only.
|
|
*
|
|
* @param[in] state Print '[x]' when !=0, print '[ ]' when 0
|
|
**************************************************************************/
|
|
static void __neorv32_rte_print_checkbox(int state) {
|
|
|
|
neorv32_uart0_putc('[');
|
|
if (state) {
|
|
neorv32_uart0_putc('x');
|
|
}
|
|
else {
|
|
neorv32_uart0_putc(' ');
|
|
}
|
|
neorv32_uart0_putc(']');
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Private function to print 32-bit number
|
|
* as 8-digit hexadecimal value (with "0x" suffix).
|
|
*
|
|
* @param[in] num Number to print as hexadecimal.
|
|
**************************************************************************/
|
|
void __neorv32_rte_print_hex_word(uint32_t num) {
|
|
|
|
static const char hex_symbols[16] = "0123456789ABCDEF";
|
|
|
|
neorv32_uart0_puts("0x");
|
|
|
|
int i;
|
|
for (i=0; i<8; i++) {
|
|
uint32_t index = (num >> (28 - 4*i)) & 0xF;
|
|
neorv32_uart0_putc(hex_symbols[index]);
|
|
}
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Private function to print 16-bit number
|
|
* as 4-digit hexadecimal value (with "0x" suffix).
|
|
*
|
|
* @param[in] num Number to print as hexadecimal.
|
|
**************************************************************************/
|
|
void __neorv32_rte_print_hex_half(uint16_t num) {
|
|
|
|
static const char hex_symbols[16] = "0123456789ABCDEF";
|
|
|
|
neorv32_uart0_puts("0x");
|
|
|
|
int i;
|
|
for (i=0; i<4; i++) {
|
|
uint32_t index = (num >> (12 - 4*i)) & 0xF;
|
|
neorv32_uart0_putc(hex_symbols[index]);
|
|
}
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Print the processor version in human-readable format.
|
|
**************************************************************************/
|
|
void neorv32_rte_print_hw_version(void) {
|
|
|
|
uint32_t i;
|
|
char tmp, cnt;
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
|
for (i=0; i<4; i++) {
|
|
|
|
tmp = (char)(neorv32_cpu_csr_read(CSR_MIMPID) >> (24 - 8*i));
|
|
|
|
// serial division
|
|
cnt = 0;
|
|
while (tmp >= 16) {
|
|
tmp = tmp - 16;
|
|
cnt++;
|
|
}
|
|
|
|
if (cnt) {
|
|
neorv32_uart0_putc('0' + cnt);
|
|
}
|
|
neorv32_uart0_putc('0' + tmp);
|
|
if (i < 3) {
|
|
neorv32_uart0_putc('.');
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Print project credits
|
|
**************************************************************************/
|
|
void neorv32_rte_print_credits(void) {
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
|
neorv32_uart0_puts("The NEORV32 RISC-V Processor, github.com/stnolting/neorv32\n"
|
|
"(c) 2023 by Dipl.-Ing. Stephan Nolting, BSD 3-Clause License\n\n");
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Print project logo
|
|
**************************************************************************/
|
|
void neorv32_rte_print_logo(void) {
|
|
|
|
const uint16_t logo_data_c[9][7] = {
|
|
{0b0000000000000000,0b0000000000000000,0b0000000000000000,0b0000000000000000,0b0000000000000000,0b0000001100000000,0b1100011000110000},
|
|
{0b0110000011000111,0b1111110001111111,0b1000011111111000,0b1100000011000111,0b1111100001111111,0b1000001100000011,0b1111111111111100},
|
|
{0b1111000011001100,0b0000000011000000,0b1100110000001100,0b1100000011001100,0b0000110011000000,0b1100001100001111,0b0000000000001111},
|
|
{0b1101100011001100,0b0000000011000000,0b1100110000001100,0b1100000011000000,0b0000110000000001,0b1000001100000011,0b0001111110001100},
|
|
{0b1100110011001111,0b1111100011000000,0b1100111111111000,0b1100000011000000,0b1111100000000110,0b0000001100001111,0b0001111110001111},
|
|
{0b1100011011001100,0b0000000011000000,0b1100110000110000,0b0110000110000000,0b0000110000011000,0b0000001100000011,0b0001111110001100},
|
|
{0b1100001111001100,0b0000000011000000,0b1100110000011000,0b0011001100001100,0b0000110001100000,0b0000001100001111,0b0000000000001111},
|
|
{0b1100000110000111,0b1111110001111111,0b1000110000001100,0b0000110000000111,0b1111100011111111,0b1100001100000011,0b1111111111111100},
|
|
{0b0000000000000000,0b0000000000000000,0b0000000000000000,0b0000000000000000,0b0000000000000000,0b0000001100000000,0b1100011000110000}
|
|
};
|
|
|
|
int u,v,w;
|
|
uint16_t tmp;
|
|
char c;
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
|
for (u=0; u<9; u++) {
|
|
neorv32_uart0_puts("\n");
|
|
for (v=0; v<7; v++) {
|
|
tmp = logo_data_c[u][v];
|
|
for (w=0; w<16; w++){
|
|
c = ' ';
|
|
if (((int16_t)tmp) < 0) { // check MSB
|
|
c = '#';
|
|
}
|
|
neorv32_uart0_putc(c);
|
|
tmp <<= 1;
|
|
}
|
|
}
|
|
}
|
|
neorv32_uart0_puts("\n");
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Print project license
|
|
**************************************************************************/
|
|
void neorv32_rte_print_license(void) {
|
|
|
|
if (neorv32_uart0_available() == 0) {
|
|
return; // cannot output anything if UART0 is not implemented
|
|
}
|
|
|
|
neorv32_uart0_puts(
|
|
"\n"
|
|
"BSD 3-Clause License\n"
|
|
"\n"
|
|
"Copyright (c) 2023, Stephan Nolting. All rights reserved.\n"
|
|
"\n"
|
|
"Redistribution and use in source and binary forms, with or without modification, are\n"
|
|
"permitted provided that the following conditions are met:\n"
|
|
"\n"
|
|
"1. Redistributions of source code must retain the above copyright notice, this list of\n"
|
|
" conditions and the following disclaimer.\n"
|
|
"\n"
|
|
"2. Redistributions in binary form must reproduce the above copyright notice, this list of\n"
|
|
" conditions and the following disclaimer in the documentation and/or other materials\n"
|
|
" provided with the distribution.\n"
|
|
"\n"
|
|
"3. Neither the name of the copyright holder nor the names of its contributors may be used to\n"
|
|
" endorse or promote products derived from this software without specific prior written\n"
|
|
" permission.\n"
|
|
"\n"
|
|
"THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\" AND ANY EXPRESS\n"
|
|
"OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF\n"
|
|
"MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE\n"
|
|
"COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\n"
|
|
"EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE\n"
|
|
"GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED\n"
|
|
"AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\n"
|
|
"NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED\n"
|
|
"OF THE POSSIBILITY OF SUCH DAMAGE.\n"
|
|
"\n"
|
|
"\n"
|
|
);
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Get MISA CSR value according to *compiler/toolchain configuration*.
|
|
*
|
|
* @return MISA content according to compiler configuration.
|
|
**************************************************************************/
|
|
uint32_t neorv32_rte_get_compiler_isa(void) {
|
|
|
|
uint32_t misa_cc = 0;
|
|
|
|
#if defined __riscv_atomic || defined __riscv_a
|
|
misa_cc |= 1 << CSR_MISA_A;
|
|
#endif
|
|
|
|
#ifdef __riscv_b
|
|
misa_cc |= 1 << CSR_MISA_B;
|
|
#endif
|
|
|
|
#if defined __riscv_compressed || defined __riscv_c
|
|
misa_cc |= 1 << CSR_MISA_C;
|
|
#endif
|
|
|
|
#if (__riscv_flen == 64) || defined __riscv_d
|
|
misa_cc |= 1 << CSR_MISA_D;
|
|
#endif
|
|
|
|
#ifdef __riscv_32e
|
|
misa_cc |= 1 << CSR_MISA_E;
|
|
#else
|
|
misa_cc |= 1 << CSR_MISA_I;
|
|
#endif
|
|
|
|
#if (__riscv_flen == 32) || defined __riscv_f
|
|
misa_cc |= 1 << CSR_MISA_F;
|
|
#endif
|
|
|
|
#if defined __riscv_mul || defined __riscv_m
|
|
misa_cc |= 1 << CSR_MISA_M;
|
|
#endif
|
|
|
|
#if (__riscv_xlen == 32)
|
|
misa_cc |= 1 << CSR_MISA_MXL_LO;
|
|
#elif (__riscv_xlen == 64)
|
|
misa_cc |= 2 << CSR_MISA_MXL_LO;
|
|
#else
|
|
misa_cc |= 3 << CSR_MISA_MXL_LO;
|
|
#endif
|
|
|
|
return misa_cc;
|
|
}
|
|
|
|
|
|
/**********************************************************************//**
|
|
* NEORV32 runtime environment: Check required ISA extensions (via compiler flags) against available ISA extensions (via MISA csr).
|
|
*
|
|
* @param[in] silent Show error message (via neorv32.uart) if isa_sw > isa_hw when = 0.
|
|
* @return MISA content according to compiler configuration.
|
|
**************************************************************************/
|
|
int neorv32_rte_check_isa(int silent) {
|
|
|
|
uint32_t misa_sw = neorv32_rte_get_compiler_isa();
|
|
uint32_t misa_hw = neorv32_cpu_csr_read(CSR_MISA);
|
|
|
|
// mask hardware features that are not used by software
|
|
uint32_t check = misa_hw & misa_sw;
|
|
|
|
if (check == misa_sw) {
|
|
return 0;
|
|
}
|
|
else {
|
|
if ((silent == 0) && (neorv32_uart0_available() != 0)) {
|
|
neorv32_uart0_printf("\nWARNING! SW_ISA (features required) vs HW_ISA (features available) mismatch!\n"
|
|
"SW_ISA = 0x%x (compiler flags)\n"
|
|
"HW_ISA = 0x%x (misa csr)\n\n", misa_sw, misa_hw);
|
|
}
|
|
return 1;
|
|
}
|
|
}
|
|
|