252 lines
13 KiB
VHDL
252 lines
13 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - Watch Dog Timer (WDT) >> #
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-- # ********************************************************************************************* #
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-- # "Bark and bite" Watchdog. The WDt will trigger a CPU interrupt when the internal 24-bit #
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-- # reaches half of the programmed timeout value ("bark") before generating a system-wide #
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-- # hardware reset when it finally reaches the full timeout value ("bite"). The internal counter #
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-- # increments at 1/4096 of the processor's main clock. #
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-- # #
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-- # Access to the control register can be permanently inhibited by setting the lock bit. This bit #
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-- # can only be cleared by a system reset. #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_wdt is
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port (
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-- host access --
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clk_i : in std_ulogic; -- global clock line
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rstn_ext_i : in std_ulogic; -- external reset line, low-active, async
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rstn_int_i : in std_ulogic; -- internal reset line, low-active, async
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addr_i : in std_ulogic_vector(31 downto 0); -- address
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rden_i : in std_ulogic; -- read enable
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wren_i : in std_ulogic; -- write enable
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data_i : in std_ulogic_vector(31 downto 0); -- data in
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data_o : out std_ulogic_vector(31 downto 0); -- data out
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ack_o : out std_ulogic; -- transfer acknowledge
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-- CPU status --
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cpu_debug_i : in std_ulogic; -- CPU is in debug mode
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cpu_sleep_i : in std_ulogic; -- CPU is in sleep mode
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-- clock generator --
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clkgen_en_o : out std_ulogic; -- enable clock generator
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clkgen_i : in std_ulogic_vector(07 downto 0);
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-- timeout event --
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irq_o : out std_ulogic; -- timeout IRQ
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rstn_o : out std_ulogic -- timeout reset, low_active, sync
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);
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end neorv32_wdt;
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architecture neorv32_wdt_rtl of neorv32_wdt is
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-- IO space: module base address --
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constant hi_abb_c : natural := index_size_f(io_size_c)-1; -- high address boundary bit
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constant lo_abb_c : natural := index_size_f(wdt_size_c); -- low address boundary bit
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-- Control register bits --
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constant ctrl_enable_c : natural := 0; -- r/w: WDT enable
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constant ctrl_lock_c : natural := 1; -- r/w: lock write access to control register when set
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constant ctrl_dben_c : natural := 2; -- r/w: allow WDT to continue operation even when CPU is in debug mode
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constant ctrl_sen_c : natural := 3; -- r/w: allow WDT to continue operation even when CPU is in sleep mode
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constant ctrl_reset_c : natural := 4; -- -/w: reset WDT if set ("feed" watchdog)
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constant ctrl_rcause_c : natural := 5; -- r/-: cause of last system reset: 0=external reset, 1=watchdog timeout
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--
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constant ctrl_timeout_lsb_c : natural := 8; -- -/w: access password LSB
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constant ctrl_timeout_msb_c : natural := 31; -- -/w: access password MSB
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-- access control --
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signal acc_en : std_ulogic; -- module access enable
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signal wren : std_ulogic;
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signal rden : std_ulogic;
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-- control register --
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type ctrl_t is record
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enable : std_ulogic; -- WDT enable
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lock : std_ulogic; -- lock write access to control register when set
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dben : std_ulogic; -- allow WDT to continue operation even when CPU is in debug mode
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sen : std_ulogic; -- allow WDT to continue operation even when CPU is in sleep mode
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reset : std_ulogic; -- reset WDT if set ("feed" watchdog)
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rcause : std_ulogic; -- cause of last system reset: 0=external reset, 1=watchdog timeout
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timeout : std_ulogic_vector(23 downto 0); -- timeout value
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end record;
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signal ctrl : ctrl_t;
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-- prescaler clock generator --
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signal prsc_tick : std_ulogic;
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-- timeout counter --
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signal cnt : std_ulogic_vector(23 downto 0); -- timeout counter
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signal cnt_started : std_ulogic;
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signal cnt_inc, cnt_inc_ff : std_ulogic; -- increment counter when set
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signal timeout_rst : std_ulogic;
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signal timeout_irq : std_ulogic;
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-- interrupt & reset generators --
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signal irq_gen_buf, hw_rstn : std_ulogic;
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begin
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-- Access Control -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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acc_en <= '1' when (addr_i(hi_abb_c downto lo_abb_c) = wdt_base_c(hi_abb_c downto lo_abb_c)) else '0';
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wren <= acc_en and wren_i;
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rden <= acc_en and rden_i;
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-- Write Access ---------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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write_access: process(rstn_int_i, clk_i)
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begin
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if (rstn_int_i = '0') then
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ctrl.enable <= '0'; -- disable WDT after reset
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ctrl.lock <= '0'; -- unlock after reset
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ctrl.dben <= '0';
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ctrl.sen <= '0';
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ctrl.reset <= '0';
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ctrl.timeout <= (others => '0');
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elsif rising_edge(clk_i) then
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ctrl.reset <= '0'; -- default
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if (wren = '1') then
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ctrl.reset <= data_i(ctrl_reset_c);
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if (ctrl.lock = '0') then -- update configuration only if not locked
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ctrl.enable <= data_i(ctrl_enable_c);
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ctrl.lock <= data_i(ctrl_lock_c) and ctrl.enable; -- lock only if already enabled
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ctrl.dben <= data_i(ctrl_dben_c);
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ctrl.sen <= data_i(ctrl_sen_c);
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ctrl.timeout <= data_i(ctrl_timeout_msb_c downto ctrl_timeout_lsb_c);
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end if;
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end if;
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end if;
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end process write_access;
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-- clock generator --
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clkgen_en_o <= ctrl.enable; -- enable clock generator
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prsc_tick <= clkgen_i(clk_div4096_c); -- clock enable tick
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-- Read Access ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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read_access: process(clk_i)
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begin
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if rising_edge(clk_i) then
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ack_o <= rden or wren;
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data_o <= (others => '0');
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if (rden = '1') then
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data_o(ctrl_enable_c) <= ctrl.enable;
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data_o(ctrl_lock_c) <= ctrl.lock;
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data_o(ctrl_dben_c) <= ctrl.dben;
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data_o(ctrl_sen_c) <= ctrl.sen;
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data_o(ctrl_rcause_c) <= ctrl.rcause;
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data_o(ctrl_timeout_msb_c downto ctrl_timeout_lsb_c) <= ctrl.timeout;
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end if;
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end if;
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end process read_access;
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-- Timeout Counter ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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wdt_counter: process(clk_i)
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begin
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if rising_edge(clk_i) then
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cnt_inc_ff <= cnt_inc;
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cnt_started <= ctrl.enable and (cnt_started or prsc_tick); -- set with next clock tick
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if (ctrl.enable = '0') or (ctrl.reset = '1') then -- watchdog disabled or reset
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cnt <= (others => '0');
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elsif (cnt_inc_ff = '1') then
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cnt <= std_ulogic_vector(unsigned(cnt) + 1);
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end if;
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end if;
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end process wdt_counter;
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-- valid counter increment? --
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cnt_inc <= '1' when (prsc_tick = '1') and (cnt_started = '1') and -- clock tick and started
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((cpu_debug_i = '0') or (ctrl.dben = '1')) and -- not in debug mode or allowed to run in debug mode
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((cpu_sleep_i = '0') or (ctrl.sen = '1')) else '0'; -- not in sleep mode or allowed to run in sleep mode
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-- timeout detection --
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timeout_irq <= '1' when (cnt_started = '1') and (cnt = ('0' & ctrl.timeout(23 downto 1))) else '0'; -- half timeout value
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timeout_rst <= '1' when (cnt_started = '1') and (cnt = ctrl.timeout(23 downto 0)) else '0'; -- full timeout value
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-- Interrupt Generator --------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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irq_generator: process(clk_i)
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begin
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if rising_edge(clk_i) then
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irq_gen_buf <= timeout_irq;
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if (irq_gen_buf = '0') and (timeout_irq = '1') and -- rising edge detector
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(ctrl.enable = '1') and (timeout_rst = '0') then -- enabled and not a HW reset
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irq_o <= '1';
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else
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irq_o <= '0';
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end if;
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end if;
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end process irq_generator;
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-- Reset Generator ------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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reset_generator: process(rstn_int_i, clk_i)
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begin
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if (rstn_int_i = '0') then
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hw_rstn <= '1';
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elsif rising_edge(clk_i) then
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if (ctrl.enable = '1') and (timeout_rst = '1') then
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hw_rstn <= '0';
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else
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hw_rstn <= '1';
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end if;
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end if;
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end process reset_generator;
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-- system wide reset --
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rstn_o <= hw_rstn;
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-- Reset Cause Indicator ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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reset_cause: process(rstn_ext_i, clk_i)
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begin
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if (rstn_ext_i = '0') then
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ctrl.rcause <= '0';
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elsif rising_edge(clk_i) then
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ctrl.rcause <= ctrl.rcause or (not hw_rstn); -- sticky-set on WDT timeout/force
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end if;
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end process reset_cause;
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end neorv32_wdt_rtl;
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