425 lines
30 KiB
VHDL
425 lines
30 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - CPU: Compressed Instructions Decoder (RISC-V "C" Extension) >> #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2023, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_cpu_decompressor is
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generic (
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FPU_ENABLE : boolean -- floating-point instruction enabled
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);
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port (
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-- instruction input --
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ci_instr16_i : in std_ulogic_vector(15 downto 0); -- compressed instruction input
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-- instruction output --
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ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
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ci_instr32_o : out std_ulogic_vector(31 downto 0) -- 32-bit decompressed instruction
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);
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end neorv32_cpu_decompressor;
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architecture neorv32_cpu_decompressor_rtl of neorv32_cpu_decompressor is
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-- compressed instruction layout --
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constant ci_opcode_lsb_c : natural := 0;
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constant ci_opcode_msb_c : natural := 1;
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constant ci_rd_3_lsb_c : natural := 2;
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constant ci_rd_3_msb_c : natural := 4;
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constant ci_rd_5_lsb_c : natural := 7;
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constant ci_rd_5_msb_c : natural := 11;
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constant ci_rs1_3_lsb_c : natural := 7;
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constant ci_rs1_3_msb_c : natural := 9;
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constant ci_rs1_5_lsb_c : natural := 7;
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constant ci_rs1_5_msb_c : natural := 11;
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constant ci_rs2_3_lsb_c : natural := 2;
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constant ci_rs2_3_msb_c : natural := 4;
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constant ci_rs2_5_lsb_c : natural := 2;
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constant ci_rs2_5_msb_c : natural := 6;
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constant ci_funct3_lsb_c : natural := 13;
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constant ci_funct3_msb_c : natural := 15;
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begin
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-- Compressed Instruction Decoder ---------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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decompressor: process(ci_instr16_i)
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variable imm20_v : std_ulogic_vector(20 downto 0);
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variable imm12_v : std_ulogic_vector(12 downto 0);
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begin
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-- defaults --
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ci_illegal_o <= '0';
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ci_instr32_o <= (others => '0');
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-- helper: 22-bit sign-extended immediate for J/JAL --
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imm20_v := (others => ci_instr16_i(12)); -- sign extension
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imm20_v(00):= '0';
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imm20_v(01):= ci_instr16_i(3);
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imm20_v(02):= ci_instr16_i(4);
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imm20_v(03):= ci_instr16_i(5);
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imm20_v(04):= ci_instr16_i(11);
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imm20_v(05):= ci_instr16_i(2);
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imm20_v(06):= ci_instr16_i(7);
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imm20_v(07):= ci_instr16_i(6);
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imm20_v(08):= ci_instr16_i(9);
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imm20_v(09):= ci_instr16_i(10);
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imm20_v(10):= ci_instr16_i(8);
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imm20_v(11):= ci_instr16_i(12);
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-- helper: 12-bit sign-extended immediate for branches --
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imm12_v := (others => ci_instr16_i(12)); -- sign extension
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imm12_v(00):= '0';
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imm12_v(01):= ci_instr16_i(3);
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imm12_v(02):= ci_instr16_i(4);
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imm12_v(03):= ci_instr16_i(10);
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imm12_v(04):= ci_instr16_i(11);
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imm12_v(05):= ci_instr16_i(2);
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imm12_v(06):= ci_instr16_i(5);
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imm12_v(07):= ci_instr16_i(6);
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imm12_v(08):= ci_instr16_i(12);
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-- actual decoder --
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case ci_instr16_i(ci_opcode_msb_c downto ci_opcode_lsb_c) is
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when "00" => -- C0: Register-Based Loads and Stores
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case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is
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when "010" | "011" => -- C.LW / C.FLW
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-- ----------------------------------------------------------------------------------------------------------
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_load_c;
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ci_instr32_o(21 downto 20) <= "00";
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ci_instr32_o(22) <= ci_instr16_i(6);
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ci_instr32_o(23) <= ci_instr16_i(10);
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ci_instr32_o(24) <= ci_instr16_i(11);
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ci_instr32_o(25) <= ci_instr16_i(12);
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ci_instr32_o(26) <= ci_instr16_i(5);
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ci_instr32_o(31 downto 27) <= (others => '0');
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_lw_c;
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); -- x8 - x15
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c); -- x8 - x15
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if (ci_instr16_i(ci_funct3_lsb_c) = '1') and (FPU_ENABLE = false) then -- C.FLW
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ci_illegal_o <= '1';
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end if;
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when "110" | "111" => -- C.SW / C.FSW
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-- ----------------------------------------------------------------------------------------------------------
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_store_c;
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ci_instr32_o(08 downto 07) <= "00";
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ci_instr32_o(09) <= ci_instr16_i(6);
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ci_instr32_o(10) <= ci_instr16_i(10);
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ci_instr32_o(11) <= ci_instr16_i(11);
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ci_instr32_o(25) <= ci_instr16_i(12);
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ci_instr32_o(26) <= ci_instr16_i(5);
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ci_instr32_o(31 downto 27) <= (others => '0');
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sw_c;
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c); -- x8 - x15
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ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "01" & ci_instr16_i(ci_rs2_3_msb_c downto ci_rs2_3_lsb_c); -- x8 - x15
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if (ci_instr16_i(ci_funct3_lsb_c) = '1') and (FPU_ENABLE = false) then -- C.FSW
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ci_illegal_o <= '1';
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end if;
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when others => -- "000": Illegal_instruction, C.ADDI4SPN; others: illegal
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-- ----------------------------------------------------------------------------------------------------------
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rd_3_msb_c downto ci_rd_3_lsb_c);
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
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ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => '0'); -- zero extend
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ci_instr32_o(instr_imm12_lsb_c + 0) <= '0';
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ci_instr32_o(instr_imm12_lsb_c + 1) <= '0';
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ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(6);
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ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
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ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(11);
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ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12);
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ci_instr32_o(instr_imm12_lsb_c + 6) <= ci_instr16_i(7);
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ci_instr32_o(instr_imm12_lsb_c + 7) <= ci_instr16_i(8);
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ci_instr32_o(instr_imm12_lsb_c + 8) <= ci_instr16_i(9);
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ci_instr32_o(instr_imm12_lsb_c + 9) <= ci_instr16_i(10);
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--
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if (ci_instr16_i(12 downto 5) = "00000000") or -- canonical illegal C instruction or C.ADDI4SPN with nzuimm = 0
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(ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) = "001") or -- C.FLS / C.LQ
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(ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) = "100") or -- reserved
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(ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) = "101") then -- C.C.FSD / C.SQ
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ci_illegal_o <= '1';
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end if;
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end case;
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when "01" => -- C1: Control Transfer Instructions, Integer Constant-Generation Instructions
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case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is
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when "101" | "001" => -- C.J, C.JAL
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-- ----------------------------------------------------------------------------------------------------------
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if (ci_instr16_i(ci_funct3_msb_c) = '1') then -- C.J
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00000"; -- discard return address
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else -- C.JAL
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00001"; -- save return address to link register
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end if;
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jal_c;
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ci_instr32_o(19 downto 12) <= imm20_v(19 downto 12);
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ci_instr32_o(20) <= imm20_v(11);
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ci_instr32_o(30 downto 21) <= imm20_v(10 downto 01);
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ci_instr32_o(31) <= imm20_v(20);
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when "110" | "111" => -- C.BEQ, C.BNEZ
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-- ----------------------------------------------------------------------------------------------------------
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if (ci_instr16_i(ci_funct3_lsb_c) = '0') then -- C.BEQ
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_beq_c;
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else -- C.BNEZ
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_bne_c;
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end if;
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_branch_c;
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c);
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ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "00000"; -- x0
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ci_instr32_o(07) <= imm12_v(11);
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ci_instr32_o(11 downto 08) <= imm12_v(04 downto 01);
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ci_instr32_o(30 downto 25) <= imm12_v(10 downto 05);
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ci_instr32_o(31) <= imm12_v(12);
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when "010" => -- C.LI
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-- ----------------------------------------------------------------------------------------------------------
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00000"; -- x0
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
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ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
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ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
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ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
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ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
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ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
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ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
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ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12);
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when "011" => -- C.LUI / C.ADDI16SP
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-- ----------------------------------------------------------------------------------------------------------
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if (ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c) = "00010") then -- C.ADDI16SP
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00010"; -- stack pointer
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ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
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ci_instr32_o(instr_imm12_lsb_c + 0) <= '0';
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ci_instr32_o(instr_imm12_lsb_c + 1) <= '0';
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ci_instr32_o(instr_imm12_lsb_c + 2) <= '0';
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ci_instr32_o(instr_imm12_lsb_c + 3) <= '0';
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ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
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ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(2);
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ci_instr32_o(instr_imm12_lsb_c + 6) <= ci_instr16_i(5);
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ci_instr32_o(instr_imm12_lsb_c + 7) <= ci_instr16_i(3);
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ci_instr32_o(instr_imm12_lsb_c + 8) <= ci_instr16_i(4);
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ci_instr32_o(instr_imm12_lsb_c + 9) <= ci_instr16_i(12);
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else -- C.LUI
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_lui_c;
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
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ci_instr32_o(instr_imm20_msb_c downto instr_imm20_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
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ci_instr32_o(instr_imm20_lsb_c + 0) <= ci_instr16_i(2);
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ci_instr32_o(instr_imm20_lsb_c + 1) <= ci_instr16_i(3);
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ci_instr32_o(instr_imm20_lsb_c + 2) <= ci_instr16_i(4);
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ci_instr32_o(instr_imm20_lsb_c + 3) <= ci_instr16_i(5);
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ci_instr32_o(instr_imm20_lsb_c + 4) <= ci_instr16_i(6);
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ci_instr32_o(instr_imm20_lsb_c + 5) <= ci_instr16_i(12);
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end if;
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if (ci_instr16_i(6 downto 2) = "00000") and (ci_instr16_i(12) = '0') then -- reserved if nzimm = 0
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ci_illegal_o <= '1';
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end if;
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when "000" => -- C.NOP (rd=0) / C.ADDI
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-- ----------------------------------------------------------------------------------------------------------
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
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ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
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ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
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ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
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ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
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ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
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ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
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ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12);
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when others => -- 100: C.SRLI, C.SRAI, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, reserved
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-- ----------------------------------------------------------------------------------------------------------
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ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c);
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ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "01" & ci_instr16_i(ci_rs1_3_msb_c downto ci_rs1_3_lsb_c);
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ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= "01" & ci_instr16_i(ci_rs2_3_msb_c downto ci_rs2_3_lsb_c);
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case ci_instr16_i(11 downto 10) is
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when "00" | "01" => -- C.SRLI, C.SRAI
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if (ci_instr16_i(10) = '0') then -- C.SRLI
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ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
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else -- C.SRAI
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ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0100000";
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end if;
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ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
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ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sr_c;
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
|
if (ci_instr16_i(12) = '1') then -- nzuimm[5] = 1 -> RV32 custom
|
|
ci_illegal_o <= '1';
|
|
end if;
|
|
when "10" => -- C.ANDI
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_and_c;
|
|
ci_instr32_o(instr_imm12_msb_c downto instr_imm12_lsb_c) <= (others => ci_instr16_i(12)); -- sign extend
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
|
ci_instr32_o(instr_imm12_lsb_c + 5) <= ci_instr16_i(12);
|
|
when others => -- "11" = register-register operation
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c;
|
|
case ci_instr16_i(6 downto 5) is
|
|
when "00" => -- C.SUB
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_subadd_c;
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0100000";
|
|
when "01" => -- C.XOR
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_xor_c;
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
|
when "10" => -- C.OR
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_or_c;
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
|
when others => -- C.AND
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_and_c;
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
|
end case;
|
|
end case;
|
|
|
|
end case;
|
|
|
|
when others => -- C2: Stack-Pointer-Based Loads and Stores, Control Transfer Instructions (or C3, which is not a RVC instruction)
|
|
case ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) is
|
|
|
|
when "000" => -- C.SLLI
|
|
-- ----------------------------------------------------------------------------------------------------------
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alui_c;
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sll_c;
|
|
ci_instr32_o(instr_funct7_msb_c downto instr_funct7_lsb_c) <= "0000000";
|
|
ci_instr32_o(instr_imm12_lsb_c + 0) <= ci_instr16_i(2);
|
|
ci_instr32_o(instr_imm12_lsb_c + 1) <= ci_instr16_i(3);
|
|
ci_instr32_o(instr_imm12_lsb_c + 2) <= ci_instr16_i(4);
|
|
ci_instr32_o(instr_imm12_lsb_c + 3) <= ci_instr16_i(5);
|
|
ci_instr32_o(instr_imm12_lsb_c + 4) <= ci_instr16_i(6);
|
|
if (ci_instr16_i(12) = '1') then -- nzuimm[5] = 1 -> RV32 custom
|
|
ci_illegal_o <= '1';
|
|
end if;
|
|
|
|
when "010" | "011" => -- C.LWSP / C.FLWSP
|
|
-- ----------------------------------------------------------------------------------------------------------
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_load_c;
|
|
ci_instr32_o(21 downto 20) <= "00";
|
|
ci_instr32_o(22) <= ci_instr16_i(4);
|
|
ci_instr32_o(23) <= ci_instr16_i(5);
|
|
ci_instr32_o(24) <= ci_instr16_i(6);
|
|
ci_instr32_o(25) <= ci_instr16_i(12);
|
|
ci_instr32_o(26) <= ci_instr16_i(2);
|
|
ci_instr32_o(27) <= ci_instr16_i(3);
|
|
ci_instr32_o(31 downto 28) <= (others => '0');
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_lw_c;
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
|
if (ci_instr16_i(ci_funct3_lsb_c) = '1') and (FPU_ENABLE = false) then -- C.FLWSP
|
|
ci_illegal_o <= '1';
|
|
end if;
|
|
|
|
when "110" | "111" => -- C.SWSP / C.FSWSP
|
|
-- ----------------------------------------------------------------------------------------------------------
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_store_c;
|
|
ci_instr32_o(08 downto 07) <= "00";
|
|
ci_instr32_o(09) <= ci_instr16_i(9);
|
|
ci_instr32_o(10) <= ci_instr16_i(10);
|
|
ci_instr32_o(11) <= ci_instr16_i(11);
|
|
ci_instr32_o(25) <= ci_instr16_i(12);
|
|
ci_instr32_o(26) <= ci_instr16_i(7);
|
|
ci_instr32_o(27) <= ci_instr16_i(8);
|
|
ci_instr32_o(31 downto 28) <= (others => '0');
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= funct3_sw_c;
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00010"; -- stack pointer
|
|
ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c);
|
|
if (ci_instr16_i(ci_funct3_lsb_c) = '1') and (FPU_ENABLE = false) then -- C.FSWSP
|
|
ci_illegal_o <= '1';
|
|
end if;
|
|
|
|
when others => -- "100": C.JR, C.JALR, C.MV, C.EBREAK, C.ADD; others: undefined
|
|
-- ----------------------------------------------------------------------------------------------------------
|
|
if (ci_instr16_i(12) = '0') then -- C.JR, C.MV
|
|
if (ci_instr16_i(6 downto 2) = "00000") then -- C.JR
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jalr_c;
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00000"; -- discard return address
|
|
else -- C.MV
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c;
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= "000";
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= "00000"; -- x0
|
|
ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c);
|
|
end if;
|
|
else -- C.EBREAK, C.JALR, C.ADD
|
|
if (ci_instr16_i(6 downto 2) = "00000") then -- C.EBREAK, C.JALR
|
|
if (ci_instr16_i(11 downto 7) = "00000") then -- C.EBREAK
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_system_c;
|
|
ci_instr32_o(instr_funct12_msb_c downto instr_funct12_lsb_c) <= funct12_ebreak_c;
|
|
else -- C.JALR
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_jalr_c;
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rs1_5_msb_c downto ci_rs1_5_lsb_c);
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= "00001"; -- save return address to link register
|
|
end if;
|
|
else -- C.ADD
|
|
ci_instr32_o(instr_opcode_msb_c downto instr_opcode_lsb_c) <= opcode_alu_c;
|
|
ci_instr32_o(instr_funct3_msb_c downto instr_funct3_lsb_c) <= "000";
|
|
ci_instr32_o(instr_rd_msb_c downto instr_rd_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
|
ci_instr32_o(instr_rs1_msb_c downto instr_rs1_lsb_c) <= ci_instr16_i(ci_rd_5_msb_c downto ci_rd_5_lsb_c);
|
|
ci_instr32_o(instr_rs2_msb_c downto instr_rs2_lsb_c) <= ci_instr16_i(ci_rs2_5_msb_c downto ci_rs2_5_lsb_c);
|
|
end if;
|
|
end if;
|
|
--
|
|
if (ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) = "001") or -- C.FLDSP / C.LQSP
|
|
(ci_instr16_i(ci_funct3_msb_c downto ci_funct3_lsb_c) = "101") then -- C.FSDSP / C.SQSP
|
|
ci_illegal_o <= '1';
|
|
end if;
|
|
|
|
end case;
|
|
|
|
end case;
|
|
end process decompressor;
|
|
|
|
|
|
end neorv32_cpu_decompressor_rtl;
|