254 lines
13 KiB
VHDL
254 lines
13 KiB
VHDL
-- #################################################################################################
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-- # << NEORV32 - Bus Switch >> #
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-- # ********************************************************************************************* #
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-- # Allows to access a single peripheral bus ("p_bus") by two controller ports. Controller port A #
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-- # ("ca_bus") has priority over controller port B ("cb_bus"). #
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-- # ********************************************************************************************* #
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-- # BSD 3-Clause License #
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-- # #
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-- # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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-- # #
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-- # Redistribution and use in source and binary forms, with or without modification, are #
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-- # permitted provided that the following conditions are met: #
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-- # #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of #
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-- # conditions and the following disclaimer. #
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-- # #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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-- # conditions and the following disclaimer in the documentation and/or other materials #
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-- # provided with the distribution. #
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-- # #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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-- # endorse or promote products derived from this software without specific prior written #
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-- # permission. #
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-- # #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE. #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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-- #################################################################################################
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library neorv32;
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use neorv32.neorv32_package.all;
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entity neorv32_busswitch is
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generic (
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PORT_CA_READ_ONLY : boolean; -- set if controller port A is read-only
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PORT_CB_READ_ONLY : boolean -- set if controller port B is read-only
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);
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port (
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-- global control --
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clk_i : in std_ulogic; -- global clock, rising edge
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rstn_i : in std_ulogic; -- global reset, low-active, async
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-- controller interface a --
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ca_bus_priv_i : in std_ulogic; -- current privilege level
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ca_bus_cached_i : in std_ulogic; -- set if cached transfer
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ca_bus_addr_i : in std_ulogic_vector(31 downto 0); -- bus access address
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ca_bus_rdata_o : out std_ulogic_vector(31 downto 0); -- bus read data
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ca_bus_wdata_i : in std_ulogic_vector(31 downto 0); -- bus write data
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ca_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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ca_bus_we_i : in std_ulogic; -- write enable
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ca_bus_re_i : in std_ulogic; -- read enable
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ca_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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ca_bus_err_o : out std_ulogic; -- bus transfer error
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-- controller interface b --
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cb_bus_priv_i : in std_ulogic; -- current privilege level
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cb_bus_cached_i : in std_ulogic; -- set if cached transfer
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cb_bus_addr_i : in std_ulogic_vector(31 downto 0); -- bus access address
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cb_bus_rdata_o : out std_ulogic_vector(31 downto 0); -- bus read data
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cb_bus_wdata_i : in std_ulogic_vector(31 downto 0); -- bus write data
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cb_bus_ben_i : in std_ulogic_vector(03 downto 0); -- byte enable
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cb_bus_we_i : in std_ulogic; -- write enable
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cb_bus_re_i : in std_ulogic; -- read enable
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cb_bus_ack_o : out std_ulogic; -- bus transfer acknowledge
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cb_bus_err_o : out std_ulogic; -- bus transfer error
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-- peripheral bus --
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p_bus_priv_o : out std_ulogic; -- current privilege level
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p_bus_cached_o : out std_ulogic; -- set if cached transfer
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p_bus_src_o : out std_ulogic; -- access source: 0 = A, 1 = B
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p_bus_addr_o : out std_ulogic_vector(31 downto 0); -- bus access address
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p_bus_rdata_i : in std_ulogic_vector(31 downto 0); -- bus read data
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p_bus_wdata_o : out std_ulogic_vector(31 downto 0); -- bus write data
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p_bus_ben_o : out std_ulogic_vector(03 downto 0); -- byte enable
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p_bus_we_o : out std_ulogic; -- write enable
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p_bus_re_o : out std_ulogic; -- read enable
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p_bus_ack_i : in std_ulogic; -- bus transfer acknowledge
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p_bus_err_i : in std_ulogic -- bus transfer error
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);
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end neorv32_busswitch;
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architecture neorv32_busswitch_rtl of neorv32_busswitch is
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-- access requests --
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signal ca_rd_req_buf, ca_wr_req_buf : std_ulogic;
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signal cb_rd_req_buf, cb_wr_req_buf : std_ulogic;
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signal ca_req_current, ca_req_buffered : std_ulogic;
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signal cb_req_current, cb_req_buffered : std_ulogic;
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-- internal bus lines --
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signal ca_bus_ack, cb_bus_ack : std_ulogic;
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signal ca_bus_err, cb_bus_err : std_ulogic;
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signal p_bus_we, p_bus_re : std_ulogic;
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-- access arbiter --
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type arbiter_state_t is (IDLE, A_BUSY, A_RETIRE, B_BUSY, B_RETIRE);
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type arbiter_t is record
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state : arbiter_state_t;
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state_nxt : arbiter_state_t;
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bus_sel : std_ulogic;
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re_trig : std_ulogic;
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we_trig : std_ulogic;
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end record;
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signal arbiter : arbiter_t;
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begin
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-- Access Arbiter -------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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arbiter_sync: process(rstn_i, clk_i)
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begin
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if (rstn_i = '0') then
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arbiter.state <= IDLE;
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ca_rd_req_buf <= '0';
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ca_wr_req_buf <= '0';
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cb_rd_req_buf <= '0';
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cb_wr_req_buf <= '0';
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elsif rising_edge(clk_i) then
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-- arbiter --
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arbiter.state <= arbiter.state_nxt;
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-- controller A requests --
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ca_rd_req_buf <= (ca_rd_req_buf or ca_bus_re_i) and (not (ca_bus_err or ca_bus_ack));
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ca_wr_req_buf <= (ca_wr_req_buf or ca_bus_we_i) and (not (ca_bus_err or ca_bus_ack)) and (not bool_to_ulogic_f(PORT_CA_READ_ONLY));
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-- controller B requests --
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cb_rd_req_buf <= (cb_rd_req_buf or cb_bus_re_i) and (not (cb_bus_err or cb_bus_ack));
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cb_wr_req_buf <= (cb_wr_req_buf or cb_bus_we_i) and (not (cb_bus_err or cb_bus_ack)) and (not bool_to_ulogic_f(PORT_CB_READ_ONLY));
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end if;
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end process arbiter_sync;
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-- any current requests? --
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ca_req_current <= (ca_bus_re_i or ca_bus_we_i) when (PORT_CA_READ_ONLY = false) else ca_bus_re_i;
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cb_req_current <= (cb_bus_re_i or cb_bus_we_i) when (PORT_CB_READ_ONLY = false) else cb_bus_re_i;
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-- any buffered requests? --
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ca_req_buffered <= (ca_rd_req_buf or ca_wr_req_buf) when (PORT_CA_READ_ONLY = false) else ca_rd_req_buf;
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cb_req_buffered <= (cb_rd_req_buf or cb_wr_req_buf) when (PORT_CB_READ_ONLY = false) else cb_rd_req_buf;
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-- Bus Arbiter ----------------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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arbiter_comb: process(arbiter, ca_req_current, cb_req_current, ca_req_buffered, cb_req_buffered,
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ca_rd_req_buf, ca_wr_req_buf, cb_rd_req_buf, cb_wr_req_buf, p_bus_ack_i, p_bus_err_i)
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begin
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-- arbiter defaults --
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arbiter.state_nxt <= arbiter.state;
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arbiter.bus_sel <= '0';
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arbiter.we_trig <= '0';
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arbiter.re_trig <= '0';
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-- state machine --
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case arbiter.state is
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when IDLE => -- port A or B access
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-- ------------------------------------------------------------
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if (ca_req_current = '1') then -- current request from controller A?
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arbiter.bus_sel <= '0'; -- access from port A
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arbiter.state_nxt <= A_BUSY;
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elsif (ca_req_buffered = '1') then -- buffered request from controller A?
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arbiter.bus_sel <= '0'; -- access from port A
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arbiter.state_nxt <= A_RETIRE;
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elsif (cb_req_current = '1') then -- buffered request from controller B?
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arbiter.bus_sel <= '1'; -- access from port B
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arbiter.state_nxt <= B_BUSY;
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elsif (cb_req_buffered = '1') then -- current request from controller B?
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arbiter.bus_sel <= '1'; -- access from port B
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arbiter.state_nxt <= B_RETIRE;
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end if;
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when A_BUSY => -- port A pending access
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-- ------------------------------------------------------------
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arbiter.bus_sel <= '0'; -- access from port A
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if (p_bus_err_i = '1') or (p_bus_ack_i = '1') then -- termination
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arbiter.state_nxt <= IDLE;
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end if;
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when A_RETIRE => -- port A trigger buffered access
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-- ------------------------------------------------------------
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arbiter.bus_sel <= '0'; -- access from port A
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arbiter.we_trig <= ca_wr_req_buf;
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arbiter.re_trig <= ca_rd_req_buf;
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arbiter.state_nxt <= A_BUSY;
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when B_BUSY => -- port B pending access
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-- ------------------------------------------------------------
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arbiter.bus_sel <= '1'; -- access from port B
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if (p_bus_err_i = '1') or (p_bus_ack_i = '1') then -- termination
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if (ca_req_buffered = '1') or (ca_req_current = '1') then -- any request from A?
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arbiter.state_nxt <= A_RETIRE;
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else
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arbiter.state_nxt <= IDLE;
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end if;
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end if;
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when B_RETIRE => -- port B trigger buffered access
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-- ------------------------------------------------------------
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arbiter.bus_sel <= '1'; -- access from port B
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arbiter.we_trig <= cb_wr_req_buf;
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arbiter.re_trig <= cb_rd_req_buf;
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arbiter.state_nxt <= B_BUSY;
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when others => -- undefined
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-- ------------------------------------------------------------
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arbiter.state_nxt <= IDLE;
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end case;
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end process arbiter_comb;
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-- Peripheral Bus Switch ------------------------------------------------------------------
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-- -------------------------------------------------------------------------------------------
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p_bus_addr_o <= ca_bus_addr_i when (arbiter.bus_sel = '0') else cb_bus_addr_i;
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p_bus_wdata_o <= cb_bus_wdata_i when (PORT_CA_READ_ONLY = true) else
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ca_bus_wdata_i when (PORT_CB_READ_ONLY = true) else
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ca_bus_wdata_i when (arbiter.bus_sel = '0') else cb_bus_wdata_i;
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p_bus_ben_o <= cb_bus_ben_i when (PORT_CA_READ_ONLY = true) else
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ca_bus_ben_i when (PORT_CB_READ_ONLY = true) else
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ca_bus_ben_i when (arbiter.bus_sel = '0') else cb_bus_ben_i;
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p_bus_cached_o <= ca_bus_cached_i when (arbiter.bus_sel = '0') else cb_bus_cached_i;
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p_bus_priv_o <= ca_bus_priv_i when (arbiter.bus_sel = '0') else cb_bus_priv_i;
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p_bus_we <= ca_bus_we_i when (arbiter.bus_sel = '0') else cb_bus_we_i;
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p_bus_re <= ca_bus_re_i when (arbiter.bus_sel = '0') else cb_bus_re_i;
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p_bus_we_o <= p_bus_we or arbiter.we_trig;
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p_bus_re_o <= p_bus_re or arbiter.re_trig;
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p_bus_src_o <= arbiter.bus_sel;
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ca_bus_rdata_o <= p_bus_rdata_i;
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cb_bus_rdata_o <= p_bus_rdata_i;
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ca_bus_ack <= p_bus_ack_i when (arbiter.bus_sel = '0') else '0';
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cb_bus_ack <= p_bus_ack_i when (arbiter.bus_sel = '1') else '0';
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ca_bus_ack_o <= ca_bus_ack;
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cb_bus_ack_o <= cb_bus_ack;
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ca_bus_err <= p_bus_err_i when (arbiter.bus_sel = '0') else '0';
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cb_bus_err <= p_bus_err_i when (arbiter.bus_sel = '1') else '0';
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ca_bus_err_o <= ca_bus_err;
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cb_bus_err_o <= cb_bus_err;
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end neorv32_busswitch_rtl;
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