93 lines
5.1 KiB
Text
93 lines
5.1 KiB
Text
<<<
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:sectnums:
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==== Watchdog Timer (WDT)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_wdt.vhd |
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| Software driver file(s): | neorv32_wdt.c |
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| | neorv32_wdt.h |
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| Top entity port: | none |
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| Configuration generics: | _IO_WDT_EN_ | implement watchdog when _true_
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| CPU interrupts: | fast IRQ channel 0 | watchdog timeout (see <<_processor_interrupts>>)
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|=======================
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**Theory of Operation**
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The watchdog (WDT) provides a last resort for safety-critical applications. The WDT provides a "bark and bite"
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concept. The timeout counter first triggers an optional CPU interrupt ("bark") when reaching half of the programmed
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interval to inform the application of the imminent timeout. When the full timeout value is reached
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a system-wide hardware reset is generated ("bite"). The internal counter has to be reset explicitly by the application
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program every now and then to prevent a timeout.
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**Configuration**
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The watchdog is enabled by setting the control register's `WDT_CTRL_EN_ bit. When this bit is cleared, the internal
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timeout counter is reset to zero and no interrupt and no system reset can be triggered.
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The internal 32-bit timeout counter is clocked at 1/4096th of the processor's main clock (f~WDT~[Hz] = f~main~[Hz] / 4096).
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Whenever this counter reaches the programmed timeout value (_WDT_CTRL_TIMEOUT_ bits in the control register) a
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hardware reset is triggered. In order to inform the application of an imminent timeout, an optional CPU interrupt is
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triggered when the timeout counter reaches **half** of the programmed timeout value.
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The watchdog is "fed" by writing `1` to the _WDT_CTRL_RESET_ control register bit, which
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will reset the internal timeout counter back to zero.
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[NOTE]
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Writing all-zero to the _WDT_CTRL_TIMEOUT_ bits will immediately trigger a system-wide reset.
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.Watchdog Interrupt
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[NOTE]
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A watchdog interrupt occurs when the watchdog is enabled and the internal counter reaches half of the programmed
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timeout value. A triggered interrupt has to be explicitly cleared by writing zero to the according <<_mip>> CSR bit.
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.Watchdog Operation during Debugging
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[IMPORTANT]
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By default the watchdog stops operation when the CPU enters debug mode and will resume normal operation after
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the CPU has left debug mode again. This will prevent an unintended watchdog timeout during a debug session. However,
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the watchdog can also be configured to keep operating even when the CPU is in debug mode by setting the control
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register's _WDT_CTRL_DBEN_ bit.
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.Watchdog Operation during CPU Sleep
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[IMPORTANT]
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By default the watchdog stops operating when the CPU enters sleep mode. However, the watchdog can also be configured
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to keep operating even when the CPU is in sleep mode by setting the control register's _WDT_CTRL_SEN_ bit.
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**Configuration Lock**
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The watchdog control register can be locked to protect the current configuration from being modified. The lock is
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activated by setting the _WDT_CTRL_LOCK_ bit. In the locked state any write access to the control register is entirely
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ignored (see table below, "writable if locked"). Read accesses to the control register as well as watchdog resets
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(by setting the _WDT_CTRL_RESET_ flag) are not affected.
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The lock bit can only be set if the WDT is already enabled (_WDT_CTRL_EN_ is set).
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The lock bit can only be cleared again by a system-wide hardware reset.
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**Cause of last Hardware Reset**
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The cause of the last system hardware reset can be determined via the _WDT_CTRL_RCAUSE_ flag. If this flag is
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zero, the processor has been reset via the external reset signal (or the on-chip debugger). If this flag is set,
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the last system reset was caused by the watchdog itself.
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**Register Map**
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.WDT register map (`struct NEORV32_WDT`)
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[cols="<2,<2,<4,^1,^1,^2,<4"]
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[options="header",grid="all"]
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Reset value | Writable if locked | Function
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.8+<| `0xffffffbc` .8+<| `NEORV32_WDT.CTRL` <|`0` _WDT_CTRL_EN_ ^| r/w ^| `0` ^| no <| watchdog enable
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<|`1 _WDT_CTRL_LOCK_ ^| r/w ^| `0` ^| no <| lock configuration when set, clears only on system reset, can only be set if enable bit is set already
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<|`2` _WDT_CTRL_DBEN_ ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in debug mode
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<|`3` _WDT_CTRL_SEN_ ^| r/w ^| `0` ^| no <| set to allow WDT to continue operation even when CPU is in sleep mode
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<|`4` _WDT_CTRL_RESET_ ^| -/w ^| - ^| yes <| reset watchdog when set, auto-clears
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<|`5` _WDT_CTRL_RCAUSE_ ^| r/- ^| `0` ^| - <| cause of last system reset: `0`=caused by external reset signal, `1`=caused by watchdog
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<|`7:6` - ^| r/- ^| - ^| - <| _reserved_, reads as zero
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<|`31:8` _WDT_CTRL_TIMEOUT_MSB_ : _WDT_CTRL_TIMEOUT_LSB_ ^| r/w ^| 0 ^| no <| 24-bit watchdog timeout value
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|=======================
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