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22 KiB
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413 lines
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Text
:sectnums:
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== Overview
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The NEORV32footnote:[Pronounced "neo-R-V-thirty-two" or "neo-risc-five-thirty-two" in its long form.] is an open-source
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RISC-V compatible processor system that is intended as *ready-to-go* auxiliary processor within a larger SoC
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designs or as stand-alone custom / customizable microcontroller.
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The system is highly configurable and provides optional common peripherals like embedded memories,
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timers, serial interfaces, general purpose IO ports and an external bus interface to connect custom IP like
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memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb
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compatible on-chip debugger accessible via JTAG.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
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are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.
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The software framework of the processor comes with application makefiles, software libraries for all CPU
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and processor features, a bootloader, a runtime environment and several example programs - including a port
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of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
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that provides hands-on tutorials to get you started.
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**Structure**
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[start=2]
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. <<_neorv32_processor_soc>>
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. <<_neorv32_central_processing_unit_cpu>>
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. <<_software_framework>>
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. <<_on_chip_debugger_ocd>>
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. <<_legal>>
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**Annotations**
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[WARNING]
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Warning
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[IMPORTANT]
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Important
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[NOTE]
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Note
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[TIP]
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Tip
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<<<
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// ####################################################################################################################
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include::rationale.adoc[]
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// ####################################################################################################################
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:sectnums:
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=== Project Key Features
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**Project**
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* all-in-one package: **CPU** + **SoC** + **Software Framework & Tooling**
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* completely described in behavioral, platform-independent VHDL - no vendor- or technology-specific primitives, attributes, macros, libraries, etc. are used at all
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* all-Verilog "version" https://github.com/stnolting/neorv32-verilog[available] (auto-generated netlist)
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* extensive configuration options for adapting the processor to the requirements of the application
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* highly https://stnolting.github.io/neorv32/ug/#_comparative_summary[extensible hardware] - on CPU, SoC and system level
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* aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
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* FPGA friendly (e.g. _all_ internal memories can be mapped to block RAM - including the register file)
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* optimized for high clock frequencies to ease timing closure and integration
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* from zero to _"hello world!"_ - completely open source and documented
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* easy to use even for FPGA/RISC-V starters – intended to _work out of the box_
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**NEORV32 CPU (the core)**
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* 32-bit `rv32i` RISC-V CPU
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* fully RISC-V ISA compatible - checked by the https://github.com/stnolting/neorv32-riscof[official RISCOF architecture tests]
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* base ISA + privileged ISA (optional) + several ISA extensions (optional)
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* option to add custom RISC-V instructions as custom ISA extension
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* rich set of customization options (ISA extensions, design goal: performance / area (/ energy), ...)
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* aims to support <<_full_virtualization>> capabilities to increase execution safety
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* official https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[RISC-V open source architecture ID]: decimal **19**; hexadecimal `0x00000013`
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**NEORV32 Processor (the SoC)**
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* highly-configurable full-scale microcontroller-like processor system
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* based on the NEORV32 CPU
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* optional standard serial interfaces (UART, TWI, SPI, 1-Wire)
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* optional timers and counters (watchdog, system timer)
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* optional general purpose IO and PWM; a native NeoPixel(c)-compatible smart LED interface
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* optional embedded memories / caches for data, instructions and bootloader
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* optional external memory interface (Wishbone / AXI4-Lite) and stream link interface (AXI4-Stream) for custom connectivity
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* optional execute_in_place (XIP) module to execute code _directly_ form external SPI flash
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* on-chip debugger compatible with OpenOCD and gdb including hardware trigger module
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**Software framework**
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* GCC-based toolchain - https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains available]; application compilation based on GNU makefiles
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* internal bootloader with serial user interface (via UART)
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* core libraries and HAL for high-level usage of the provided functions and peripherals
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* processor-specific runtime environment and several example programs
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* doxygen-based documentation of the software framework; a deployed version is available at https://stnolting.github.io/neorv32/sw/files.html
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* FreeRTOS port + demos available
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[TIP]
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For more in-depth details regarding the feature provided by he hardware see the according sections:
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<<_neorv32_central_processing_unit_cpu>> and <<_neorv32_processor_soc>>.
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**Extensibility and Customization**
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The NEORV32 processor was designed to ease customization and extensibility and provides several options for adding
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application-specific custom hardware modules and accelerators. The three most common options for adding custom
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on-chip modules are listed below.
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* <<_processor_external_memory_interface_wishbone_axi4_lite>> for processor-external modules
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* <<_custom_functions_subsystem_cfs>> for tightly-coupled processor-internal co-processors
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* <<_custom_functions_unit_cfu>> for custom RISC-V instructions
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[TIP]
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A more detailed comparison of the extension/customization options can be found in section
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https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules[Adding Custom Hardware Modules]
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of the user guide.
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<<<
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// ####################################################################################################################
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:sectnums:
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=== Project Folder Structure
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...................................
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neorv32 - Project home folder
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│
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├docs - Project documentation
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│├datasheet - AsciiDoc sources for the NEORV32 data sheet
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│├figures - Figures and logos
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│├icons - Misc. symbols
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│├references - Data sheets and RISC-V specs.
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│└userguide - AsciiDoc sources for the NEORV32 user guide
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│
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├rtl - VHDL sources
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│├core - Core sources of the CPU & SoC
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││└mem - SoC-internal memories (default architectures)
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│├processor_templates - Pre-configured SoC wrappers
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│├system_integration - System wrappers for advanced connectivity
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│└test_setups - Minimal test setup "SoCs" used in the User Guide
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│
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├sim - Simulation files (see User Guide)
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│
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└sw - Software framework
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├bootloader - Sources of the processor-internal bootloader
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├common - Linker script, crt0.S start-up code and central makefile
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├example - Example programs for the core and the SoC modules
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│└...
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├lib - Processor core library
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│├include - Header files (*.h)
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│└source - Source files (*.c)
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├image_gen - Helper program to generate NEORV32 executables
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├ocd_firmware - Firmware for the on-chip debugger's "park loop"
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├openocd - OpenOCD configuration files
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└svd - Processor system view description file (CMSIS-SVD)
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...................................
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<<<
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// ####################################################################################################################
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:sectnums:
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=== VHDL File Hierarchy
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All necessary VHDL hardware description files are located in the project's `rtl/core` folder. The top entity
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of the entire processor including all the required configuration generics is **`neorv32_top.vhd`**.
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[IMPORTANT]
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All core VHDL files from the list below have to be assigned to a new design library named **`neorv32`**. Additional
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files, like alternative top entities, can be assigned to any library.
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...................................
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neorv32_top.vhd - NEORV32 Processor top entity
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│
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├neorv32_fifo.vhd - General purpose FIFO component
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├neorv32_package.vhd - Processor/CPU main VHDL package file
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│
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├neorv32_cpu.vhd - NEORV32 CPU top entity
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│├neorv32_cpu_alu.vhd - Arithmetic/logic unit
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││├neorv32_cpu_cp_bitmanip.vhd - Bit-manipulation co-processor (B ext.)
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││├neorv32_cpu_cp_cfu.vhd - Custom functions (instruction) co-processor (Zxcfu ext.)
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││├neorv32_cpu_cp_fpu.vhd - Floating-point co-processor (Zfinx ext.)
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││├neorv32_cpu_cp_muldiv.vhd - Mul/Div co-processor (M ext.)
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││└neorv32_cpu_cp_shifter.vhd - Bit-shift co-processor (base ISA)
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│├neorv32_cpu_bus.vhd - Load/store unit + physical memory protection
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│├neorv32_cpu_control.vhd - CPU control, exception system and CSRs
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││└neorv32_cpu_decompressor.vhd - Compressed instructions decoder
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│└neorv32_cpu_regfile.vhd - Data register file
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│
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├neorv32_boot_rom.vhd - Bootloader ROM
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│└neorv32_bootloader_image.vhd - Bootloader ROM memory image
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├neorv32_busswitch.vhd - Processor bus switch for CPU buses (I&D)
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├neorv32_bus_keeper.vhd - Processor-internal bus monitor
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├neorv32_cfs.vhd - Custom functions subsystem
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├neorv32_debug_dm.vhd - on-chip debugger: debug module
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├neorv32_debug_dtm.vhd - on-chip debugger: debug transfer module
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├neorv32_dmem.entity.vhd - Processor-internal data memory (entity-only!)
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├neorv32_gpio.vhd - General purpose input/output port unit
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├neorv32_gptmr.vhd - General purpose 32-bit timer
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├neorv32_icache.vhd - Processor-internal instruction cache
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├neorv32_imem.entity.vhd - Processor-internal instruction memory (entity-only!)
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│└neor32_application_image.vhd - IMEM application initialization image
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├neorv32_mtime.vhd - Machine system timer
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├neorv32_neoled.vhd - NeoPixel (TM) compatible smart LED interface
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├neorv32_onewire.vhd - One-Wire serial interface controller
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├neorv32_pwm.vhd - Pulse-width modulation controller
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├neorv32_slink.vhd - Stream link controller
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├neorv32_spi.vhd - Serial peripheral interface controller
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├neorv32_sysinfo.vhd - System configuration information memory
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├neorv32_trng.vhd - True random number generator
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├neorv32_twi.vhd - Two wire serial interface controller
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├neorv32_uart.vhd - Universal async. receiver/transmitter
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├neorv32_wdt.vhd - Watchdog timer
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├neorv32_wishbone.vhd - External (Wishbone) bus interface
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├neorv32_xip.vhd - Execute in place module
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├neorv32_xirq.vhd - External interrupt controller
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│
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├mem/neorv32_dmem.default.vhd - _Default_ data memory (architecture-only)
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└mem/neorv32_imem.default.vhd - _Default_ instruction memory (architecture-only)
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...................................
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[NOTE]
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The processor-internal instruction and data memories (IMEM and DMEM) are split into two design files each:
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a plain entity definition (`neorv32_*mem.entity.vhd`) and the actual architecture definition
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(`mem/neorv32_*mem.default.vhd`). The `*.default.vhd` architecture definitions from `rtl/core/mem` provide a _generic_ and
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_platform independent_ memory design that (should) infers embedded memory blocks. You can replace/modify the architecture
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source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
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and/or timing.
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<<<
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// ####################################################################################################################
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:sectnums:
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=== FPGA Implementation Results
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This section shows _exemplary_ FPGA implementation results for the NEORV32 CPU and NEORV32 Processor modules.
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Note that certain configuration options might also have an impact on other configuration options. Furthermore,
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this report cannot cover all possible option combinations. Hence, the presented implementation results are
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just _exemplary_. If not otherwise mentioned all implementations use the default generic configurations.
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:sectnums:
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==== CPU
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[cols="<2,<8"]
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[grid="topbot"]
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|=======================
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| HW version: | `1.7.8.5`
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| Top entity: | `rtl/core/neorv32_cpu.vhd`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| Toolchain: | Quartus Prime Lite 21.1
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| Constraints: | **no timing constraints**, "_balanced optimization_", f~max~ from "_Slow 1200mV 0C Model_"
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|=======================
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[cols="<6,>1,>1,>1,>1,>1"]
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[options="header",grid="rows"]
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|=======================
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| CPU ISA Configuration | LEs | FFs | MEM bits | DSPs | _f~max~_
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| `rv32e` | 720 | 360 | 512 | 0 | 130 MHz
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| `rv32i` | 724 | 364 | 1024 | 0 | 130 MHz
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| `rv32i_Zicsr` | 1223 | 607 | 1024 | 0 | 130 MHz
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| `rv32i_Zicsr_Zicntr` | 1578 | 773 | 1024 | 0 | 130 MHz
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| `rv32im_Zicsr_Zicntr` | 2087 | 983 | 1024 | 0 | 130 MHz
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| `rv32imc_Zicsr_Zicntr` | 2338 | 992 | 1024 | 0 | 130 MHz
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| `rv32imcb_Zicsr_Zicntr` | 3175 | 1247 | 1024 | 0 | 130 MHz
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| `rv32imcbu_Zicsr_Zicntr` | 3186 | 1254 | 1024 | 0 | 130 MHz
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| `rv32imcbu_Zicsr_Zicntr_Zifencei` | 3187 | 1254 | 1024 | 0 | 130 MHz
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| `rv32imcbu_Zicsr_Zicntr_Zifencei_Zfinx` | 4450 | 1906 | 1024 | 7 | 123 MHz
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| `rv32imcbu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 4825 | 2018 | 1024 | 7 | 123 MHz
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|=======================
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[NOTE]
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The table above does not show _all_ CPU ISA extensions. More sophisticated and application-specific
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options like PMP and HMP are not included in this overview.
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.Goal-Driven Optimization
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[TIP]
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The CPU provides further options to reduce the area footprint (for example by constraining the CPU-internal
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counter sizes) or to increase performance (for example by using a barrel-shifter; at cost of extra hardware).
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See section <<_processor_top_entity_generics>> for more information. Also, take a look at the User Guide section
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https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration[Application-Specific Processor Configuration].
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:sectnums:
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==== Processor - Modules
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[cols="<2,<8"]
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[grid="topbot"]
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|=======================
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| HW version: | `1.6.8.3++`
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| Top entity: | `rtl/core/neorv32_top.vhd`
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| FPGA: | Intel Cyclone IV E `EP4CE22F17C6`
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| Toolchain: | Quartus Prime Lite 21.1
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| Constraints: | **no timing constraints**, "_balanced optimization_"
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|=======================
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.Hardware utilization by processor module (mandatory modules highlighted in **bold**)
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[cols="<2,<8,>1,>1,>2,>1"]
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[options="header",grid="rows"]
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|=======================
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| Module | Description | LEs | FFs | MEM bits | DSPs
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| Boot ROM | Bootloader ROM (4kB) | 3 | 2 | 32768 | 0
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| **BUSKEEPER** | Processor-internal bus monitor | 28 | 15 | 0 | 0
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| **BUSSWITCH** | Bus multiplexer for CPU instr. and data interface | 69 | 8 | 0 | 0
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| CFS | Custom functions subsystem footnote:[Resource utilization depends on custom design logic.] | - | - | - | -
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| DM | On-chip debugger - debug module | 391 | 220 | 0 | 0
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| DTM | On-chip debugger - debug transfer module (JTAG) | 259 | 221 | 0 | 0
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| DMEM | Processor-internal data memory (8kB) | 18 | 2 | 65536 | 0
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| GPIO | General purpose input/output ports | 102 | 98 | 0 | 0
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| GPTMR | General Purpose Timer | 153 | 105 | 0 | 0
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| iCACHE | Instruction cache (2x4 blocks, 64 bytes per block) | 417 | 297 | 4096 | 0
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| IMEM | Processor-internal instruction memory (16kB) | 12 | 2 | 131072 | 0
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| MTIME | Machine system timer | 345 | 166 | 0 | 0
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| NEOLED | Smart LED Interface (NeoPixel/WS28128) (FIFO_depth=1) | 227 | 184 | 0 | 0
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| ONEWIRE | 1-wire interface | 107 | 77 | 0 | 0
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| PWM | Pulse_width modulation controller (8 channels) | 128 | 117 | 0 | 0
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| SLINK | Stream link interface (2xRX, 2xTX, FIFO_depth=1) | 136 | 116 | 0 | 0
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| SPI | Serial peripheral interface | 114 | 94 | 0 | 0
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| **SYSINFO** | System configuration information memory | 13 | 11 | 0 | 0
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| TRNG | True random number generator | 89 | 79 | 0 | 0
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| TWI | Two-wire interface | 77 | 43 | 0 | 0
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| UART0, UART1 | Universal asynchronous receiver/transmitter 0/1 (FIFO_depth=1) | 195 | 143 | 0 | 0
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| WDT | Watchdog timer | 61 | 46 | 0 | 0
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| WISHBONE | External memory interface | 120 | 112 | 0 | 0
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| XIP | Execute in place module | 318 | 244 | 0 | 0
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| XIRQ | External interrupt controller (32 channels) | 245 | 200 | 0 | 0
|
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|=======================
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|
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[NOTE]
|
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Note that not all IOs were actually connected to FPGA pins (for example some GPIO inputs and outputs)
|
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when generating these reports.
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|
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|
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:sectnums:
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==== Processor - Exemplary Setups
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[cols="<2,<8"]
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[grid="topbot"]
|
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|=======================
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| HW version: | `1.7.7.3`
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| CPU: | `rv32imcu_Zicsr_Zicnt_DEBUG` + `FST_MUL` + `FAST_SHIFT`
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| Peripherals: | `UART0` + `MTIME` + `GPIO`
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| FPGA: | Xilinx Artix-7 `xc7a35ticsg324-1L`
|
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| Toolchain: | Xilinx Vivado 2019.2
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| Constraints: | clock constrained to 150 MHz, default/standard synthesis & implementation settings
|
||
|=======================
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[cols="^1,^1,^1,^1,^1"]
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[options="header",grid="rows"]
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|=======================
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| LUTs | FFs | BRAMs | DSPs | Clock
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| 2488 | 1807 | 7 | 4 | 150 MHz
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|=======================
|
||
|
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.Exemplary Setups
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[TIP]
|
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Check out the `neorv32-setups` repository (on GitHub: https://github.com/stnolting/neorv32-setups),
|
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which provides several demo setups and community projects for various FPGA boards and toolchains.
|
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|
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|
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<<<
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// ####################################################################################################################
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:sectnums:
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=== CPU Performance
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|
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The performance of the NEORV32 was tested and evaluated using the https://www.eembc.org/coremark/[Core Mark CPU benchmark].
|
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This benchmark focuses on testing the capabilities of the CPU core itself rather than the performance of the whole
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system. The according sources can be found in the `sw/example/coremark` folder.
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|
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.Dhrystone
|
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[TIP]
|
||
A very simple port of the Dhrystone benchmark is also available in `sw/example/dhrystone`.
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||
|
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The resulting CoreMark score is defined as CoreMark iterations per second.
|
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The execution time is determined via the RISC-V `[m]cycle[h]` CSRs. The relative CoreMark score is
|
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defined as CoreMark score divided by the CPU's clock frequency in MHz.
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|
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.Configuration
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[cols="<2,<8"]
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[grid="topbot"]
|
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|=======================
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| HW version: | `1.5.7.10`
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| Hardware: | 32kB int. IMEM, 16kB int. DMEM, no caches, 100MHz clock
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| CoreMark: | 2000 iterations, MEM_METHOD is MEM_STACK
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| Compiler: | RISCV32-GCC 10.2.0 (compiled with `march=rv32i mabi=ilp32`)
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| Compiler flags: | default (with `-O3`), see makefile
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|=======================
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|
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.CoreMark results
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[cols="<4,^1,^1,^1"]
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[options="header",grid="rows"]
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|=======================
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| CPU | CoreMark Score | CoreMarks/MHz | Average CPI
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| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04**
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| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34**
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| _performance_ (`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54**
|
||
|=======================
|
||
|
||
[NOTE]
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||
The "_performance_" CPU configuration uses the <<_fast_mul_en>> and <<_fast_shift_en>> options.
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||
|
||
The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of
|
||
several consecutive micro operations.
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||
The average CPI (cycles per instruction) depends on the instruction mix of a specific applications and also on
|
||
the available CPU extensions. The average CPI is computed by dividing the total number of required clock cycles
|
||
(only the timed core to avoid distortion due to IO wait cycles) by the number of executed instructions
|
||
(`[m]instret[h]` CSRs). More information regarding the execution time of each implemented instruction can be found in
|
||
chapter <<_instruction_timing>>.
|