branchement
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12 changed files with 26656 additions and 8 deletions
BIN
Rapport/branchement/memory_cycles.png
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Rapport/branchement/memory_cycles.png
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Rapport/branchement/plot.py
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Rapport/branchement/plot.py
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import matplotlib.pyplot as plt
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from sklearn.linear_model import LinearRegression
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import numpy as np
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Y_B2 = [36, 3876, 7716, 11556, 15396, 19236, 23076, 26916, 30756]
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Y_B3 = [97, 36786, 84655, 135454, 191580, 247876, 304307, 365937, 427737]
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YA_B2 = [28, 2124, 4199, 6345, 8380, 10441, 12525, 14607, 16690]
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YA_B3 = [36, 4106 , 8161 , 12071, 16060, 20056 , 24096, 28115, 32068]
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X = [0, 128, 256, 384, 512, 640, 768, 896, 1024]
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plt.scatter(X, Y_B2, color="b", label="RISCV Branchement 1/2")
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plt.scatter(X, Y_B3, color="b", marker="x", label="Branchement 1/3")
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plt.scatter(X, YA_B2, color="r", label="ARM Branchement 1/2")
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plt.scatter(X, YA_B3, color="r",marker="x", label="ARM Branchement 1/3")
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x = np.array(X).reshape(-1, 1)
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y = np.array(Y_B2).reshape(-1, 1)
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y2 = np.array(YA_B2).reshape(-1, 1)
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reg = LinearRegression().fit(x, y)
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reg2 = LinearRegression().fit(x, y2)
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print("score obtenu : " + str(reg.score(x, y)))
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print("score obtenu : " + str(reg2.score(x, y2)))
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print("attente à zéro : {}".format(reg.intercept_))
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print("attente à zéro : {}".format(reg2.intercept_))
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x_lin = [0, max(X)]
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y_lin = [reg.predict(np.array([0]).reshape(-1, 1)), reg.predict(np.array([x_lin[1]]).reshape(-1, 1))]
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y_lin2 = [reg2.predict(np.array([0]).reshape(-1, 1)), reg2.predict(np.array([x_lin[1]]).reshape(-1, 1))]
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y_lin = [y_lin[0][0][0], y_lin[1][0][0]]
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y_lin2 = [y_lin2[0][0][0], y_lin2[1][0][0]]
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plt.plot(x_lin, y_lin, color = "b", label="RegLin score : {:.4f}".format(reg.score(x, y)))
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plt.plot(x_lin, y_lin2, color = "r", label="RegLin score : {:.4f}".format(reg2.score(x, y2)))
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plt.xlim([0, 1024])
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plt.ylim([50, 450000])
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plt.legend()
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plt.title("Cycles d'exécution en fonction de n_max")
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plt.ylabel("Cycles")
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plt.xlabel("N_max")
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plt.savefig("memory_cycles.png")
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plt.show()
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26485
branchement/debug.txt
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branchement/debug.txt
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branchement/main.bin
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branchement/main.bin
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branchement/main.c
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branchement/main.c
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// #################################################################################################
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// # << NEORV32 - "Hello World" Demo Program >> #
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// # ********************************************************************************************* #
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// # BSD 3-Clause License #
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// # #
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// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #
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// # #
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// # Redistribution and use in source and binary forms, with or without modification, are #
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// # permitted provided that the following conditions are met: #
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// # #
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// # 1. Redistributions of source code must retain the above copyright notice, this list of #
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// # conditions and the following disclaimer. #
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// # #
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// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #
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// # conditions and the following disclaimer in the documentation and/or other materials #
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// # provided with the distribution. #
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// # #
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// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #
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// # endorse or promote products derived from this software without specific prior written #
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// # permission. #
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// # #
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// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #
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// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #
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// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #
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// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #
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// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #
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// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #
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// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #
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// # OF THE POSSIBILITY OF SUCH DAMAGE. #
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// # ********************************************************************************************* #
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// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #
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// #################################################################################################
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/**********************************************************************//**
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* @file hello_world/main.c
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* @author Stephan Nolting
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* @brief Classic 'hello world' demo program.
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**************************************************************************/
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#include <neorv32.h>
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/**********************************************************************//**
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* @name User configuration
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**************************************************************************/
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/**@{*/
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/** UART BAUD rate */
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#define BAUD_RATE 19200
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/**@}*/
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void fn_b2(uint32_t N, uint32_t *y){
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for(uint32_t i=0; i<N; i++){
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if(i%2) y[i] = 0;
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else y[i] = 1;
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}
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}
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void fn_b3(uint32_t N, uint32_t *x, uint32_t *y){
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for(uint32_t i=0; i<N; i++){
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if(i%3) y[i] = 0;
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else y[i] = 1;
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}
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}
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/**********************************************************************//**
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* Main function; prints some fancy stuff via UART.
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*
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* @note This program requires the UART interface to be synthesized.
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*
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* @return 0 if execution was successful
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**************************************************************************/
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int main() {
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long Begin_Time, End_Time, User_Time;
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uint32_t n_max;
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// capture all exceptions and give debug info via UART
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// this is not required, but keeps us safe
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neorv32_rte_setup();
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// init UART at default baud rate, no parity bits, no HW flow control
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neorv32_uart0_setup(BAUD_RATE, PARITY_NONE, FLOW_CONTROL_NONE);
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// check available hardware extensions and compare with compiler flags
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neorv32_rte_check_isa(0); // silent = 0 -> show message if isa mismatch
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// say hello
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neorv32_uart0_puts("Memory management cycles measure :\n");
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neorv32_uart0_printf("NEORV32: Freq = %u\n",NEORV32_SYSINFO.CLK);
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uint32_t y[1024];
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uint32_t x;
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for(n_max=0; n_max<1024+1; n_max+=128){
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Begin_Time = (long)neorv32_mtime_get_time();
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for(uint32_t j=0; j<10; j++){
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fn_b2(n_max, y);
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}
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End_Time = (long)neorv32_mtime_get_time();
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User_Time = End_Time - Begin_Time;
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neorv32_uart0_printf("NEORV32: B2 mean cycles N = %u : %u\n",n_max, (uint32_t)User_Time/10);
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Begin_Time = (long)neorv32_mtime_get_time();
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for(uint32_t j=0; j<10; j++){
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fn_b3(n_max, &x, y);
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}
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End_Time = (long)neorv32_mtime_get_time();
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User_Time = End_Time - Begin_Time;
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neorv32_uart0_printf("NEORV32: B3 mean cycles N = %u : %u\n",n_max, (uint32_t)User_Time/10);
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}
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neorv32_uart0_puts("end:\n");
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return 0;
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}
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branchement/main.c.o
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branchement/main.c.o
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branchement/main.elf
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branchement/main.elf
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branchement/makefile
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branchement/makefile
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# Modify this variable to fit your NEORV32 setup (neorv32 home folder)
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NEORV32_HOME ?= ../neorv32
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include $(NEORV32_HOME)/sw/common/common.mk
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branchement/neorv32_exe.bin
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branchement/neorv32_exe.bin
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proj_quartus/db/bootloarder_1.quiproj.8167.rdr.flock
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proj_quartus/db/bootloarder_1.quiproj.8167.rdr.flock
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Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition
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Quartus_Version = Version 22.1std.0 Build 915 10/25/2022 SC Standard Edition
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Version_Index = 553882368
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Version_Index = 553882368
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Creation_Time = Thu Mar 9 16:31:59 2023
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Creation_Time = Thu Mar 9 18:25:24 2023
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start_full_compilation:s:00:02:10
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start_full_compilation:s
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start_analysis_synthesis:s:00:00:19-start_full_compilation
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start_assembler:s-start_full_compilation
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start_analysis_elaboration:s-start_full_compilation
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start_timing_analyzer:s-start_full_compilation
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start_fitter:s:00:01:31-start_full_compilation
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start_eda_netlist_writer:s-start_full_compilation
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start_assembler:s:00:00:08-start_full_compilation
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start_timing_analyzer:s:00:00:10-start_full_compilation
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start_eda_netlist_writer:s:00:00:02-start_full_compilation
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