318 lines
9.3 KiB
C
318 lines
9.3 KiB
C
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/*
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* QEMU lowRISC Ibex Timer device
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*
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* Copyright (c) 2021 Western Digital
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*
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* For details check the documentation here:
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* https://docs.opentitan.org/hw/ip/rv_timer/doc/
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "hw/timer/ibex_timer.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "target/riscv/cpu.h"
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#include "migration/vmstate.h"
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REG32(ALERT_TEST, 0x00)
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FIELD(ALERT_TEST, FATAL_FAULT, 0, 1)
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REG32(CTRL, 0x04)
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FIELD(CTRL, ACTIVE, 0, 1)
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REG32(CFG0, 0x100)
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FIELD(CFG0, PRESCALE, 0, 12)
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FIELD(CFG0, STEP, 16, 8)
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REG32(LOWER0, 0x104)
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REG32(UPPER0, 0x108)
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REG32(COMPARE_LOWER0, 0x10C)
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REG32(COMPARE_UPPER0, 0x110)
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REG32(INTR_ENABLE, 0x114)
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FIELD(INTR_ENABLE, IE_0, 0, 1)
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REG32(INTR_STATE, 0x118)
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FIELD(INTR_STATE, IS_0, 0, 1)
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REG32(INTR_TEST, 0x11C)
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FIELD(INTR_TEST, T_0, 0, 1)
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static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq)
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{
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return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
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timebase_freq, NANOSECONDS_PER_SECOND);
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}
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static void ibex_timer_update_irqs(IbexTimerState *s)
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{
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CPUState *cs = qemu_get_cpu(0);
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RISCVCPU *cpu = RISCV_CPU(cs);
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uint64_t value = s->timer_compare_lower0 |
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((uint64_t)s->timer_compare_upper0 << 32);
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uint64_t next, diff;
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uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
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if (!(s->timer_ctrl & R_CTRL_ACTIVE_MASK)) {
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/* Timer isn't active */
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return;
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}
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/* Update the CPUs mtimecmp */
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cpu->env.timecmp = value;
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if (cpu->env.timecmp <= now) {
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/*
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* If the mtimecmp was in the past raise the interrupt now.
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*/
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qemu_irq_raise(s->m_timer_irq);
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if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
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s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
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qemu_set_irq(s->irq, true);
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}
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return;
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}
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/* Setup a timer to trigger the interrupt in the future */
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qemu_irq_lower(s->m_timer_irq);
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qemu_set_irq(s->irq, false);
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diff = cpu->env.timecmp - now;
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next = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
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muldiv64(diff,
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NANOSECONDS_PER_SECOND,
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s->timebase_freq);
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if (next < qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
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/* We overflowed the timer, just set it as large as we can */
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timer_mod(cpu->env.timer, 0x7FFFFFFFFFFFFFFF);
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} else {
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timer_mod(cpu->env.timer, next);
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}
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}
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static void ibex_timer_cb(void *opaque)
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{
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IbexTimerState *s = opaque;
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qemu_irq_raise(s->m_timer_irq);
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if (s->timer_intr_enable & R_INTR_ENABLE_IE_0_MASK) {
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s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
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qemu_set_irq(s->irq, true);
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}
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}
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static void ibex_timer_reset(DeviceState *dev)
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{
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IbexTimerState *s = IBEX_TIMER(dev);
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CPUState *cpu = qemu_get_cpu(0);
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CPURISCVState *env = cpu->env_ptr;
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env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
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&ibex_timer_cb, s);
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env->timecmp = 0;
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s->timer_ctrl = 0x00000000;
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s->timer_cfg0 = 0x00010000;
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s->timer_compare_lower0 = 0xFFFFFFFF;
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s->timer_compare_upper0 = 0xFFFFFFFF;
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s->timer_intr_enable = 0x00000000;
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s->timer_intr_state = 0x00000000;
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ibex_timer_update_irqs(s);
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}
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static uint64_t ibex_timer_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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IbexTimerState *s = opaque;
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uint64_t now = cpu_riscv_read_rtc(s->timebase_freq);
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uint64_t retvalue = 0;
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switch (addr >> 2) {
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case R_ALERT_TEST:
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qemu_log_mask(LOG_GUEST_ERROR,
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"Attempted to read ALERT_TEST, a write only register");
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break;
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case R_CTRL:
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retvalue = s->timer_ctrl;
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break;
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case R_CFG0:
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retvalue = s->timer_cfg0;
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break;
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case R_LOWER0:
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retvalue = now;
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break;
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case R_UPPER0:
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retvalue = now >> 32;
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break;
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case R_COMPARE_LOWER0:
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retvalue = s->timer_compare_lower0;
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break;
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case R_COMPARE_UPPER0:
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retvalue = s->timer_compare_upper0;
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break;
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case R_INTR_ENABLE:
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retvalue = s->timer_intr_enable;
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break;
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case R_INTR_STATE:
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retvalue = s->timer_intr_state;
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break;
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case R_INTR_TEST:
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qemu_log_mask(LOG_GUEST_ERROR,
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"Attempted to read INTR_TEST, a write only register");
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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return 0;
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}
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return retvalue;
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}
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static void ibex_timer_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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IbexTimerState *s = opaque;
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uint32_t val = val64;
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switch (addr >> 2) {
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case R_ALERT_TEST:
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qemu_log_mask(LOG_UNIMP, "Alert triggering not supported");
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break;
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case R_CTRL:
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s->timer_ctrl = val;
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break;
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case R_CFG0:
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qemu_log_mask(LOG_UNIMP, "Changing prescale or step not supported");
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s->timer_cfg0 = val;
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break;
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case R_LOWER0:
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qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
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break;
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case R_UPPER0:
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qemu_log_mask(LOG_UNIMP, "Changing timer value is not supported");
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break;
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case R_COMPARE_LOWER0:
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s->timer_compare_lower0 = val;
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ibex_timer_update_irqs(s);
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break;
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case R_COMPARE_UPPER0:
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s->timer_compare_upper0 = val;
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ibex_timer_update_irqs(s);
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break;
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case R_INTR_ENABLE:
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s->timer_intr_enable = val;
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break;
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case R_INTR_STATE:
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/* Write 1 to clear */
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s->timer_intr_state &= ~val;
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break;
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case R_INTR_TEST:
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if (s->timer_intr_enable & val & R_INTR_ENABLE_IE_0_MASK) {
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s->timer_intr_state |= R_INTR_STATE_IS_0_MASK;
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qemu_set_irq(s->irq, true);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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}
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}
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static const MemoryRegionOps ibex_timer_ops = {
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.read = ibex_timer_read,
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.write = ibex_timer_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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};
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static int ibex_timer_post_load(void *opaque, int version_id)
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{
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IbexTimerState *s = opaque;
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ibex_timer_update_irqs(s);
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return 0;
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}
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static const VMStateDescription vmstate_ibex_timer = {
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.name = TYPE_IBEX_TIMER,
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.version_id = 2,
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.minimum_version_id = 2,
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.post_load = ibex_timer_post_load,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(timer_ctrl, IbexTimerState),
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VMSTATE_UINT32(timer_cfg0, IbexTimerState),
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VMSTATE_UINT32(timer_compare_lower0, IbexTimerState),
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VMSTATE_UINT32(timer_compare_upper0, IbexTimerState),
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VMSTATE_UINT32(timer_intr_enable, IbexTimerState),
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VMSTATE_UINT32(timer_intr_state, IbexTimerState),
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VMSTATE_END_OF_LIST()
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}
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};
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static Property ibex_timer_properties[] = {
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DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void ibex_timer_init(Object *obj)
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{
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IbexTimerState *s = IBEX_TIMER(obj);
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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memory_region_init_io(&s->mmio, obj, &ibex_timer_ops, s,
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TYPE_IBEX_TIMER, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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}
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static void ibex_timer_realize(DeviceState *dev, Error **errp)
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{
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IbexTimerState *s = IBEX_TIMER(dev);
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qdev_init_gpio_out(dev, &s->m_timer_irq, 1);
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}
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static void ibex_timer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = ibex_timer_reset;
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dc->vmsd = &vmstate_ibex_timer;
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dc->realize = ibex_timer_realize;
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device_class_set_props(dc, ibex_timer_properties);
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}
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static const TypeInfo ibex_timer_info = {
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.name = TYPE_IBEX_TIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IbexTimerState),
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.instance_init = ibex_timer_init,
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.class_init = ibex_timer_class_init,
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};
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static void ibex_timer_register_types(void)
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{
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type_register_static(&ibex_timer_info);
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}
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type_init(ibex_timer_register_types)
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