284 lines
11 KiB
C
284 lines
11 KiB
C
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#include "qemu/osdep.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/pci-host/gpex.h"
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#include "hw/arm/virt.h"
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#include "hw/pci/pci_bus.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pcie_host.h"
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#include "hw/acpi/cxl.h"
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static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq)
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{
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Aml *method, *crs;
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int i, slot_no;
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/* Declare the PCI Routing Table. */
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Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS);
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for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) {
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for (i = 0; i < PCI_NUM_PINS; i++) {
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int gsi = (i + slot_no) % PCI_NUM_PINS;
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Aml *pkg = aml_package(4);
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aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF));
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aml_append(pkg, aml_int(i));
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aml_append(pkg, aml_name("GSI%d", gsi));
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aml_append(pkg, aml_int(0));
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aml_append(rt_pkg, pkg);
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}
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}
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aml_append(dev, aml_name_decl("_PRT", rt_pkg));
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/* Create GSI link device */
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for (i = 0; i < PCI_NUM_PINS; i++) {
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uint32_t irqs = irq + i;
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Aml *dev_gsi = aml_device("GSI%d", i);
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aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
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aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i)));
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crs = aml_resource_template();
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aml_append(crs,
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aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
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AML_EXCLUSIVE, &irqs, 1));
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aml_append(dev_gsi, aml_name_decl("_PRS", crs));
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crs = aml_resource_template();
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aml_append(crs,
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aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
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AML_EXCLUSIVE, &irqs, 1));
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aml_append(dev_gsi, aml_name_decl("_CRS", crs));
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method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
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aml_append(dev_gsi, method);
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aml_append(dev, dev_gsi);
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}
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}
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static void acpi_dsdt_add_pci_osc(Aml *dev)
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{
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Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf;
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/* Declare an _OSC (OS Control Handoff) method */
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aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
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aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
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method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
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aml_append(method,
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aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
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/* PCI Firmware Specification 3.0
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* 4.5.1. _OSC Interface for PCI Host Bridge Devices
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* The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
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* identified by the Universal Unique IDentifier (UUID)
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* 33DB4D5B-1FF7-401C-9657-7441C03DD766
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*/
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UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
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ifctx = aml_if(aml_equal(aml_arg(0), UUID));
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aml_append(ifctx,
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aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
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aml_append(ifctx,
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aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
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aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
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aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
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/*
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* Allow OS control for all 5 features:
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* PCIeHotplug SHPCHotplug PME AER PCIeCapability.
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*/
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aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F),
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aml_name("CTRL")));
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ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
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aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08),
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aml_name("CDW1")));
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aml_append(ifctx, ifctx1);
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ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
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aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10),
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aml_name("CDW1")));
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aml_append(ifctx, ifctx1);
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aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
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aml_append(ifctx, aml_return(aml_arg(3)));
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aml_append(method, ifctx);
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elsectx = aml_else();
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aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4),
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aml_name("CDW1")));
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aml_append(elsectx, aml_return(aml_arg(3)));
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aml_append(method, elsectx);
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aml_append(dev, method);
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method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
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/* PCI Firmware Specification 3.0
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* 4.6.1. _DSM for PCI Express Slot Information
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* The UUID in _DSM in this context is
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* {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
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*/
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UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
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ifctx = aml_if(aml_equal(aml_arg(0), UUID));
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ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
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uint8_t byte_list[1] = {1};
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buf = aml_buffer(1, byte_list);
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aml_append(ifctx1, aml_return(buf));
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aml_append(ifctx, ifctx1);
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aml_append(method, ifctx);
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byte_list[0] = 0;
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buf = aml_buffer(1, byte_list);
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aml_append(method, aml_return(buf));
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aml_append(dev, method);
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}
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void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg)
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{
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int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN;
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Aml *method, *crs, *dev, *rbuf;
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PCIBus *bus = cfg->bus;
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CrsRangeSet crs_range_set;
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CrsRangeEntry *entry;
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int i;
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/* start to construct the tables for pxb */
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crs_range_set_init(&crs_range_set);
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if (bus) {
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QLIST_FOREACH(bus, &bus->child, sibling) {
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uint8_t bus_num = pci_bus_num(bus);
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uint8_t numa_node = pci_bus_numa_node(bus);
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bool is_cxl = pci_bus_is_cxl(bus);
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if (!pci_bus_is_root(bus)) {
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continue;
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}
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/*
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* 0 - (nr_pcie_buses - 1) is the bus range for the main
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* host-bridge and it equals the MIN of the
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* busNr defined for pxb-pcie.
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*/
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if (bus_num < nr_pcie_buses) {
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nr_pcie_buses = bus_num;
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}
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dev = aml_device("PC%.02X", bus_num);
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if (is_cxl) {
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struct Aml *pkg = aml_package(2);
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aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016")));
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aml_append(pkg, aml_eisaid("PNP0A08"));
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aml_append(pkg, aml_eisaid("PNP0A03"));
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aml_append(dev, aml_name_decl("_CID", pkg));
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} else {
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aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
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}
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aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
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aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
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aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device")));
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aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
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if (numa_node != NUMA_NODE_UNASSIGNED) {
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aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
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}
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acpi_dsdt_add_pci_route_table(dev, cfg->irq);
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/*
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* Resources defined for PXBs are composed by the folling parts:
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* 1. The resources the pci-brige/pcie-root-port need.
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* 2. The resources the devices behind pxb need.
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*/
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crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set,
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cfg->pio.base, 0, 0, 0);
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aml_append(dev, aml_name_decl("_CRS", crs));
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if (is_cxl) {
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build_cxl_osc_method(dev);
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} else {
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acpi_dsdt_add_pci_osc(dev);
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}
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aml_append(scope, dev);
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}
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}
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/* tables for the main */
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dev = aml_device("%s", "PCI0");
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aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
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aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
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aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
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aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
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aml_append(dev, aml_name_decl("_UID", aml_int(0)));
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aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
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aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
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acpi_dsdt_add_pci_route_table(dev, cfg->irq);
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method = aml_method("_CBA", 0, AML_NOTSERIALIZED);
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aml_append(method, aml_return(aml_int(cfg->ecam.base)));
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aml_append(dev, method);
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/*
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* At this point crs_range_set has all the ranges used by pci
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* busses *other* than PCI0. These ranges will be excluded from
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* the PCI0._CRS.
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*/
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rbuf = aml_resource_template();
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aml_append(rbuf,
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aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
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nr_pcie_buses));
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if (cfg->mmio32.size) {
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crs_replace_with_free_ranges(crs_range_set.mem_ranges,
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cfg->mmio32.base,
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cfg->mmio32.base + cfg->mmio32.size - 1);
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for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
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entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
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aml_append(rbuf,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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entry->base, entry->limit,
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0x0000, entry->limit - entry->base + 1));
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}
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}
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if (cfg->pio.size) {
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crs_replace_with_free_ranges(crs_range_set.io_ranges,
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0x0000,
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cfg->pio.size - 1);
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for (i = 0; i < crs_range_set.io_ranges->len; i++) {
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entry = g_ptr_array_index(crs_range_set.io_ranges, i);
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aml_append(rbuf,
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aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
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AML_ENTIRE_RANGE, 0x0000, entry->base,
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entry->limit, cfg->pio.base,
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entry->limit - entry->base + 1));
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}
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}
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if (cfg->mmio64.size) {
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crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
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cfg->mmio64.base,
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cfg->mmio64.base + cfg->mmio64.size - 1);
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for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
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entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
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aml_append(rbuf,
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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entry->base,
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entry->limit, 0x0000,
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entry->limit - entry->base + 1));
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}
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}
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aml_append(dev, aml_name_decl("_CRS", rbuf));
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acpi_dsdt_add_pci_osc(dev);
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Aml *dev_res0 = aml_device("%s", "RES0");
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aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02")));
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crs = aml_resource_template();
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aml_append(crs,
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aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000,
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cfg->ecam.base,
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cfg->ecam.base + cfg->ecam.size - 1,
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0x0000,
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cfg->ecam.size));
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aml_append(dev_res0, aml_name_decl("_CRS", crs));
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aml_append(dev, dev_res0);
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aml_append(scope, dev);
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crs_range_set_free(&crs_range_set);
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}
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