281 lines
8.2 KiB
C
281 lines
8.2 KiB
C
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/*
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* CTU CAN FD PCI device emulation
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* http://canbus.pages.fel.cvut.cz/
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*
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* Copyright (c) 2019 Jan Charvat (jancharvat.charvat@gmail.com)
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*
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* Based on Kvaser PCI CAN device (SJA1000 based) emulation implemented by
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* Jin Yang and Pavel Pisa
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/event_notifier.h"
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#include "qemu/module.h"
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#include "qemu/thread.h"
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#include "qemu/sockets.h"
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#include "qapi/error.h"
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#include "chardev/char.h"
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#include "hw/irq.h"
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#include "hw/pci/pci.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#include "net/can_emu.h"
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#include "ctucan_core.h"
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#define TYPE_CTUCAN_PCI_DEV "ctucan_pci"
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typedef struct CtuCanPCIState CtuCanPCIState;
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DECLARE_INSTANCE_CHECKER(CtuCanPCIState, CTUCAN_PCI_DEV,
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TYPE_CTUCAN_PCI_DEV)
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#define CTUCAN_PCI_CORE_COUNT 2
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#define CTUCAN_PCI_CORE_RANGE 0x10000
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#define CTUCAN_PCI_BAR_COUNT 2
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#define CTUCAN_PCI_BYTES_PER_CORE 0x4000
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#ifndef PCI_VENDOR_ID_TEDIA
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#define PCI_VENDOR_ID_TEDIA 0x1760
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#endif
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#define PCI_DEVICE_ID_TEDIA_CTUCAN_VER21 0xff00
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#define CTUCAN_BAR0_RANGE 0x8000
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#define CTUCAN_BAR0_CTUCAN_ID 0x0000
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#define CTUCAN_BAR0_CRA_BASE 0x4000
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#define CYCLONE_IV_CRA_A2P_IE (0x0050)
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#define CTUCAN_WITHOUT_CTUCAN_ID 0
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#define CTUCAN_WITH_CTUCAN_ID 1
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struct CtuCanPCIState {
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/*< private >*/
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PCIDevice dev;
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/*< public >*/
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MemoryRegion ctucan_io[CTUCAN_PCI_BAR_COUNT];
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CtuCanCoreState ctucan_state[CTUCAN_PCI_CORE_COUNT];
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qemu_irq irq;
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char *model; /* The model that support, only SJA1000 now. */
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CanBusState *canbus[CTUCAN_PCI_CORE_COUNT];
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};
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static void ctucan_pci_reset(DeviceState *dev)
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{
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CtuCanPCIState *d = CTUCAN_PCI_DEV(dev);
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int i;
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for (i = 0 ; i < CTUCAN_PCI_CORE_COUNT; i++) {
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ctucan_hardware_reset(&d->ctucan_state[i]);
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}
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}
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static uint64_t ctucan_pci_id_cra_io_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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if (addr >= 4) {
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return 0;
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}
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uint64_t tmp = 0xC0000000 + CTUCAN_PCI_CORE_COUNT;
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tmp >>= ((addr & 3) << 3);
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if (size < 8) {
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tmp &= ((uint64_t)1 << (size << 3)) - 1;
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}
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return tmp;
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}
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static void ctucan_pci_id_cra_io_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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}
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static uint64_t ctucan_pci_cores_io_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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CtuCanPCIState *d = opaque;
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CtuCanCoreState *s;
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hwaddr core_num = addr / CTUCAN_PCI_BYTES_PER_CORE;
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if (core_num >= CTUCAN_PCI_CORE_COUNT) {
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return 0;
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}
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s = &d->ctucan_state[core_num];
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return ctucan_mem_read(s, addr % CTUCAN_PCI_BYTES_PER_CORE, size);
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}
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static void ctucan_pci_cores_io_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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{
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CtuCanPCIState *d = opaque;
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CtuCanCoreState *s;
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hwaddr core_num = addr / CTUCAN_PCI_BYTES_PER_CORE;
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if (core_num >= CTUCAN_PCI_CORE_COUNT) {
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return;
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}
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s = &d->ctucan_state[core_num];
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return ctucan_mem_write(s, addr % CTUCAN_PCI_BYTES_PER_CORE, data, size);
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}
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static const MemoryRegionOps ctucan_pci_id_cra_io_ops = {
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.read = ctucan_pci_id_cra_io_read,
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.write = ctucan_pci_id_cra_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static const MemoryRegionOps ctucan_pci_cores_io_ops = {
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.read = ctucan_pci_cores_io_read,
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.write = ctucan_pci_cores_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl.min_access_size = 1,
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.impl.max_access_size = 4,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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};
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static void ctucan_pci_realize(PCIDevice *pci_dev, Error **errp)
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{
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CtuCanPCIState *d = CTUCAN_PCI_DEV(pci_dev);
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uint8_t *pci_conf;
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int i;
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pci_conf = pci_dev->config;
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pci_conf[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
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d->irq = pci_allocate_irq(&d->dev);
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for (i = 0 ; i < CTUCAN_PCI_CORE_COUNT; i++) {
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ctucan_init(&d->ctucan_state[i], d->irq);
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}
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for (i = 0 ; i < CTUCAN_PCI_CORE_COUNT; i++) {
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if (ctucan_connect_to_bus(&d->ctucan_state[i], d->canbus[i]) < 0) {
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error_setg(errp, "ctucan_connect_to_bus failed");
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return;
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}
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}
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memory_region_init_io(&d->ctucan_io[0], OBJECT(d),
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&ctucan_pci_id_cra_io_ops, d,
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"ctucan_pci-core0", CTUCAN_BAR0_RANGE);
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memory_region_init_io(&d->ctucan_io[1], OBJECT(d),
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&ctucan_pci_cores_io_ops, d,
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"ctucan_pci-core1", CTUCAN_PCI_CORE_RANGE);
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for (i = 0 ; i < CTUCAN_PCI_BAR_COUNT; i++) {
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pci_register_bar(&d->dev, i, PCI_BASE_ADDRESS_MEM_MASK & 0,
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&d->ctucan_io[i]);
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}
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}
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static void ctucan_pci_exit(PCIDevice *pci_dev)
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{
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CtuCanPCIState *d = CTUCAN_PCI_DEV(pci_dev);
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int i;
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for (i = 0 ; i < CTUCAN_PCI_CORE_COUNT; i++) {
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ctucan_disconnect(&d->ctucan_state[i]);
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}
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qemu_free_irq(d->irq);
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}
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static const VMStateDescription vmstate_ctucan_pci = {
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.name = "ctucan_pci",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(dev, CtuCanPCIState),
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VMSTATE_STRUCT(ctucan_state[0], CtuCanPCIState, 0, vmstate_ctucan,
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CtuCanCoreState),
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#if CTUCAN_PCI_CORE_COUNT >= 2
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VMSTATE_STRUCT(ctucan_state[1], CtuCanPCIState, 0, vmstate_ctucan,
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CtuCanCoreState),
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#endif
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VMSTATE_END_OF_LIST()
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}
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};
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static void ctucan_pci_instance_init(Object *obj)
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{
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CtuCanPCIState *d = CTUCAN_PCI_DEV(obj);
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object_property_add_link(obj, "canbus0", TYPE_CAN_BUS,
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(Object **)&d->canbus[0],
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qdev_prop_allow_set_link_before_realize, 0);
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#if CTUCAN_PCI_CORE_COUNT >= 2
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object_property_add_link(obj, "canbus1", TYPE_CAN_BUS,
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(Object **)&d->canbus[1],
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qdev_prop_allow_set_link_before_realize, 0);
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#endif
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}
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static void ctucan_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = ctucan_pci_realize;
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k->exit = ctucan_pci_exit;
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k->vendor_id = PCI_VENDOR_ID_TEDIA;
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k->device_id = PCI_DEVICE_ID_TEDIA_CTUCAN_VER21;
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k->revision = 0x00;
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k->class_id = 0x000c09;
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k->subsystem_vendor_id = PCI_VENDOR_ID_TEDIA;
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k->subsystem_id = PCI_DEVICE_ID_TEDIA_CTUCAN_VER21;
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dc->desc = "CTU CAN PCI";
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dc->vmsd = &vmstate_ctucan_pci;
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set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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dc->reset = ctucan_pci_reset;
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}
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static const TypeInfo ctucan_pci_info = {
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.name = TYPE_CTUCAN_PCI_DEV,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(CtuCanPCIState),
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.class_init = ctucan_pci_class_init,
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.instance_init = ctucan_pci_instance_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void ctucan_pci_register_types(void)
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{
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type_register_static(&ctucan_pci_info);
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}
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type_init(ctucan_pci_register_types)
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