712 lines
14 KiB
C
712 lines
14 KiB
C
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/* gdb.c --- sim interface to GDB.
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Copyright (C) 2005-2022 Free Software Foundation, Inc.
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Contributed by Red Hat, Inc.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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/* This must come before any other includes. */
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#include "defs.h"
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#include <stdio.h>
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#include <assert.h>
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#include <signal.h>
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#include <stdlib.h>
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#include <string.h>
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#include <ctype.h>
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#include "ansidecl.h"
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#include "libiberty.h"
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#include "sim/callback.h"
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#include "sim/sim.h"
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#include "gdb/signals.h"
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#include "gdb/sim-m32c.h"
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#include "cpu.h"
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#include "mem.h"
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#include "load.h"
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#include "syscalls.h"
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#ifdef TIMER_A
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#include "timer_a.h"
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#endif
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/* I don't want to wrap up all the minisim's data structures in an
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object and pass that around. That'd be a big change, and neither
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GDB nor run needs that ability.
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So we just have one instance, that lives in global variables, and
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each time we open it, we re-initialize it. */
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struct sim_state
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{
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const char *message;
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};
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static struct sim_state the_minisim = {
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"This is the sole m32c minisim instance. See libsim.a's global variables."
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};
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static int is_open;
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind,
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struct host_callback_struct *callback,
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struct bfd *abfd, char * const *argv)
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{
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setbuf (stdout, 0);
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if (is_open)
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fprintf (stderr, "m32c minisim: re-opened sim\n");
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/* The 'run' interface doesn't use this function, so we don't care
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about KIND; it's always SIM_OPEN_DEBUG. */
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if (kind != SIM_OPEN_DEBUG)
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fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
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kind);
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if (abfd)
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m32c_set_mach (bfd_get_mach (abfd));
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/* We can use ABFD, if non-NULL to select the appropriate
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architecture. But we only support the r8c right now. */
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set_callbacks (callback);
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/* We don't expect any command-line arguments. */
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init_mem ();
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init_regs ();
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is_open = 1;
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return &the_minisim;
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}
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static void
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check_desc (SIM_DESC sd)
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{
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if (sd != &the_minisim)
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fprintf (stderr, "m32c minisim: desc != &the_minisim\n");
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}
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void
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sim_close (SIM_DESC sd, int quitting)
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{
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check_desc (sd);
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/* Not much to do. At least free up our memory. */
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init_mem ();
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is_open = 0;
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}
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static bfd *
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open_objfile (const char *filename)
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{
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bfd *prog = bfd_openr (filename, 0);
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if (!prog)
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{
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fprintf (stderr, "Can't read %s\n", filename);
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return 0;
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}
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if (!bfd_check_format (prog, bfd_object))
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{
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fprintf (stderr, "%s not a m32c program\n", filename);
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return 0;
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}
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return prog;
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}
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SIM_RC
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sim_load (SIM_DESC sd, const char *prog, struct bfd * abfd, int from_tty)
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{
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check_desc (sd);
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if (!abfd)
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abfd = open_objfile (prog);
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if (!abfd)
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return SIM_RC_FAIL;
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m32c_load (abfd);
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return SIM_RC_OK;
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}
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SIM_RC
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sim_create_inferior (SIM_DESC sd, struct bfd * abfd,
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char * const *argv, char * const *env)
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{
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check_desc (sd);
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if (abfd)
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m32c_load (abfd);
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return SIM_RC_OK;
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}
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int
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sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
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{
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check_desc (sd);
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if (mem == 0)
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return 0;
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mem_get_blk ((int) mem, buf, length);
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return length;
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}
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int
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sim_write (SIM_DESC sd, SIM_ADDR mem, const unsigned char *buf, int length)
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{
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check_desc (sd);
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mem_put_blk ((int) mem, buf, length);
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return length;
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}
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/* Read the LENGTH bytes at BUF as an little-endian value. */
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static DI
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get_le (unsigned char *buf, int length)
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{
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DI acc = 0;
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while (--length >= 0)
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acc = (acc << 8) + buf[length];
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return acc;
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}
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/* Store VAL as a little-endian value in the LENGTH bytes at BUF. */
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static void
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put_le (unsigned char *buf, int length, DI val)
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{
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int i;
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for (i = 0; i < length; i++)
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{
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buf[i] = val & 0xff;
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val >>= 8;
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}
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}
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static int
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check_regno (enum m32c_sim_reg regno)
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{
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return 0 <= regno && regno < m32c_sim_reg_num_regs;
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}
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static size_t
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mask_size (int addr_mask)
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{
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switch (addr_mask)
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{
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case 0xffff:
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return 2;
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case 0xfffff:
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case 0xffffff:
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return 3;
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default:
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fprintf (stderr,
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"m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
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addr_mask);
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return sizeof (addr_mask);
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}
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}
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static size_t
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reg_size (enum m32c_sim_reg regno)
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{
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switch (regno)
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{
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case m32c_sim_reg_r0_bank0:
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case m32c_sim_reg_r1_bank0:
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case m32c_sim_reg_r2_bank0:
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case m32c_sim_reg_r3_bank0:
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case m32c_sim_reg_r0_bank1:
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case m32c_sim_reg_r1_bank1:
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case m32c_sim_reg_r2_bank1:
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case m32c_sim_reg_r3_bank1:
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case m32c_sim_reg_flg:
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case m32c_sim_reg_svf:
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return 2;
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case m32c_sim_reg_a0_bank0:
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case m32c_sim_reg_a1_bank0:
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case m32c_sim_reg_fb_bank0:
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case m32c_sim_reg_sb_bank0:
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case m32c_sim_reg_a0_bank1:
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case m32c_sim_reg_a1_bank1:
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case m32c_sim_reg_fb_bank1:
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case m32c_sim_reg_sb_bank1:
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case m32c_sim_reg_usp:
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case m32c_sim_reg_isp:
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return mask_size (addr_mask);
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case m32c_sim_reg_pc:
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case m32c_sim_reg_intb:
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case m32c_sim_reg_svp:
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case m32c_sim_reg_vct:
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return mask_size (membus_mask);
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case m32c_sim_reg_dmd0:
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case m32c_sim_reg_dmd1:
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return 1;
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case m32c_sim_reg_dct0:
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case m32c_sim_reg_dct1:
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case m32c_sim_reg_drc0:
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case m32c_sim_reg_drc1:
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return 2;
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case m32c_sim_reg_dma0:
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case m32c_sim_reg_dma1:
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case m32c_sim_reg_dsa0:
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case m32c_sim_reg_dsa1:
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case m32c_sim_reg_dra0:
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case m32c_sim_reg_dra1:
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return 3;
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default:
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fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
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regno);
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return -1;
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}
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}
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int
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sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
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{
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size_t size;
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check_desc (sd);
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if (!check_regno (regno))
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return 0;
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size = reg_size (regno);
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if (length == size)
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{
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DI val;
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switch (regno)
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{
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case m32c_sim_reg_r0_bank0:
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val = regs.r[0].r_r0;
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break;
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case m32c_sim_reg_r1_bank0:
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val = regs.r[0].r_r1;
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break;
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case m32c_sim_reg_r2_bank0:
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val = regs.r[0].r_r2;
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break;
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case m32c_sim_reg_r3_bank0:
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val = regs.r[0].r_r3;
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break;
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case m32c_sim_reg_a0_bank0:
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val = regs.r[0].r_a0;
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break;
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case m32c_sim_reg_a1_bank0:
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val = regs.r[0].r_a1;
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break;
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case m32c_sim_reg_fb_bank0:
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val = regs.r[0].r_fb;
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break;
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case m32c_sim_reg_sb_bank0:
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val = regs.r[0].r_sb;
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break;
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case m32c_sim_reg_r0_bank1:
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val = regs.r[1].r_r0;
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break;
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case m32c_sim_reg_r1_bank1:
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val = regs.r[1].r_r1;
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break;
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case m32c_sim_reg_r2_bank1:
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val = regs.r[1].r_r2;
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break;
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case m32c_sim_reg_r3_bank1:
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val = regs.r[1].r_r3;
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break;
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case m32c_sim_reg_a0_bank1:
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val = regs.r[1].r_a0;
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break;
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case m32c_sim_reg_a1_bank1:
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val = regs.r[1].r_a1;
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break;
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case m32c_sim_reg_fb_bank1:
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val = regs.r[1].r_fb;
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break;
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case m32c_sim_reg_sb_bank1:
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val = regs.r[1].r_sb;
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break;
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case m32c_sim_reg_usp:
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val = regs.r_usp;
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break;
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case m32c_sim_reg_isp:
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val = regs.r_isp;
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break;
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case m32c_sim_reg_pc:
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val = regs.r_pc;
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break;
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case m32c_sim_reg_intb:
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val = regs.r_intbl * 65536 + regs.r_intbl;
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break;
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case m32c_sim_reg_flg:
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val = regs.r_flags;
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break;
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/* These registers aren't implemented by the minisim. */
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case m32c_sim_reg_svf:
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case m32c_sim_reg_svp:
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case m32c_sim_reg_vct:
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case m32c_sim_reg_dmd0:
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case m32c_sim_reg_dmd1:
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case m32c_sim_reg_dct0:
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case m32c_sim_reg_dct1:
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case m32c_sim_reg_drc0:
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case m32c_sim_reg_drc1:
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case m32c_sim_reg_dma0:
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case m32c_sim_reg_dma1:
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case m32c_sim_reg_dsa0:
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case m32c_sim_reg_dsa1:
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case m32c_sim_reg_dra0:
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|
|
case m32c_sim_reg_dra1:
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
default:
|
||
|
|
fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
|
||
|
|
regno);
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
put_le (buf, length, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
return size;
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
|
||
|
|
{
|
||
|
|
size_t size;
|
||
|
|
|
||
|
|
check_desc (sd);
|
||
|
|
|
||
|
|
if (!check_regno (regno))
|
||
|
|
return -1;
|
||
|
|
|
||
|
|
size = reg_size (regno);
|
||
|
|
|
||
|
|
if (length == size)
|
||
|
|
{
|
||
|
|
DI val = get_le (buf, length);
|
||
|
|
|
||
|
|
switch (regno)
|
||
|
|
{
|
||
|
|
case m32c_sim_reg_r0_bank0:
|
||
|
|
regs.r[0].r_r0 = val & 0xffff;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_r1_bank0:
|
||
|
|
regs.r[0].r_r1 = val & 0xffff;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_r2_bank0:
|
||
|
|
regs.r[0].r_r2 = val & 0xffff;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_r3_bank0:
|
||
|
|
regs.r[0].r_r3 = val & 0xffff;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_a0_bank0:
|
||
|
|
regs.r[0].r_a0 = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_a1_bank0:
|
||
|
|
regs.r[0].r_a1 = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_fb_bank0:
|
||
|
|
regs.r[0].r_fb = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_sb_bank0:
|
||
|
|
regs.r[0].r_sb = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_r0_bank1:
|
||
|
|
regs.r[1].r_r0 = val & 0xffff;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_r1_bank1:
|
||
|
|
regs.r[1].r_r1 = val & 0xffff;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_r2_bank1:
|
||
|
|
regs.r[1].r_r2 = val & 0xffff;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_r3_bank1:
|
||
|
|
regs.r[1].r_r3 = val & 0xffff;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_a0_bank1:
|
||
|
|
regs.r[1].r_a0 = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_a1_bank1:
|
||
|
|
regs.r[1].r_a1 = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_fb_bank1:
|
||
|
|
regs.r[1].r_fb = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_sb_bank1:
|
||
|
|
regs.r[1].r_sb = val & addr_mask;
|
||
|
|
break;
|
||
|
|
|
||
|
|
case m32c_sim_reg_usp:
|
||
|
|
regs.r_usp = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_isp:
|
||
|
|
regs.r_isp = val & addr_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_pc:
|
||
|
|
regs.r_pc = val & membus_mask;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_intb:
|
||
|
|
regs.r_intbl = (val & membus_mask) & 0xffff;
|
||
|
|
regs.r_intbh = (val & membus_mask) >> 16;
|
||
|
|
break;
|
||
|
|
case m32c_sim_reg_flg:
|
||
|
|
regs.r_flags = val & 0xffff;
|
||
|
|
break;
|
||
|
|
|
||
|
|
/* These registers aren't implemented by the minisim. */
|
||
|
|
case m32c_sim_reg_svf:
|
||
|
|
case m32c_sim_reg_svp:
|
||
|
|
case m32c_sim_reg_vct:
|
||
|
|
case m32c_sim_reg_dmd0:
|
||
|
|
case m32c_sim_reg_dmd1:
|
||
|
|
case m32c_sim_reg_dct0:
|
||
|
|
case m32c_sim_reg_dct1:
|
||
|
|
case m32c_sim_reg_drc0:
|
||
|
|
case m32c_sim_reg_drc1:
|
||
|
|
case m32c_sim_reg_dma0:
|
||
|
|
case m32c_sim_reg_dma1:
|
||
|
|
case m32c_sim_reg_dsa0:
|
||
|
|
case m32c_sim_reg_dsa1:
|
||
|
|
case m32c_sim_reg_dra0:
|
||
|
|
case m32c_sim_reg_dra1:
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
default:
|
||
|
|
fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
|
||
|
|
regno);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return size;
|
||
|
|
}
|
||
|
|
|
||
|
|
static volatile int stop;
|
||
|
|
static enum sim_stop reason;
|
||
|
|
static int siggnal;
|
||
|
|
|
||
|
|
|
||
|
|
/* Given a signal number used by the M32C bsp (that is, newlib),
|
||
|
|
return a target signal number used by GDB. */
|
||
|
|
static int
|
||
|
|
m32c_signal_to_target (int m32c)
|
||
|
|
{
|
||
|
|
switch (m32c)
|
||
|
|
{
|
||
|
|
case 4:
|
||
|
|
return GDB_SIGNAL_ILL;
|
||
|
|
|
||
|
|
case 5:
|
||
|
|
return GDB_SIGNAL_TRAP;
|
||
|
|
|
||
|
|
case 10:
|
||
|
|
return GDB_SIGNAL_BUS;
|
||
|
|
|
||
|
|
case 11:
|
||
|
|
return GDB_SIGNAL_SEGV;
|
||
|
|
|
||
|
|
case 24:
|
||
|
|
return GDB_SIGNAL_XCPU;
|
||
|
|
|
||
|
|
case 2:
|
||
|
|
return GDB_SIGNAL_INT;
|
||
|
|
|
||
|
|
case 8:
|
||
|
|
return GDB_SIGNAL_FPE;
|
||
|
|
|
||
|
|
case 6:
|
||
|
|
return GDB_SIGNAL_ABRT;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/* Take a step return code RC and set up the variables consulted by
|
||
|
|
sim_stop_reason appropriately. */
|
||
|
|
static void
|
||
|
|
handle_step (int rc)
|
||
|
|
{
|
||
|
|
if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc))
|
||
|
|
{
|
||
|
|
reason = sim_stopped;
|
||
|
|
siggnal = GDB_SIGNAL_TRAP;
|
||
|
|
}
|
||
|
|
else if (M32C_STOPPED (rc))
|
||
|
|
{
|
||
|
|
reason = sim_stopped;
|
||
|
|
siggnal = m32c_signal_to_target (M32C_STOP_SIG (rc));
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
assert (M32C_EXITED (rc));
|
||
|
|
reason = sim_exited;
|
||
|
|
siggnal = M32C_EXIT_STATUS (rc);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
void
|
||
|
|
sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
|
||
|
|
{
|
||
|
|
check_desc (sd);
|
||
|
|
|
||
|
|
if (sig_to_deliver != 0)
|
||
|
|
{
|
||
|
|
fprintf (stderr,
|
||
|
|
"Warning: the m32c minisim does not implement "
|
||
|
|
"signal delivery yet.\n" "Resuming with no signal.\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
if (step)
|
||
|
|
{
|
||
|
|
handle_step (decode_opcode ());
|
||
|
|
#ifdef TIMER_A
|
||
|
|
update_timer_a ();
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
/* We don't clear 'stop' here, because then we would miss
|
||
|
|
interrupts that arrived on the way here. Instead, we clear
|
||
|
|
the flag in sim_stop_reason, after GDB has disabled the
|
||
|
|
interrupt signal handler. */
|
||
|
|
for (;;)
|
||
|
|
{
|
||
|
|
int rc;
|
||
|
|
|
||
|
|
if (stop)
|
||
|
|
{
|
||
|
|
stop = 0;
|
||
|
|
reason = sim_stopped;
|
||
|
|
siggnal = GDB_SIGNAL_INT;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
rc = decode_opcode ();
|
||
|
|
#ifdef TIMER_A
|
||
|
|
update_timer_a ();
|
||
|
|
#endif
|
||
|
|
|
||
|
|
if (!M32C_STEPPED (rc))
|
||
|
|
{
|
||
|
|
handle_step (rc);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
m32c_sim_restore_console ();
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
sim_stop (SIM_DESC sd)
|
||
|
|
{
|
||
|
|
stop = 1;
|
||
|
|
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p)
|
||
|
|
{
|
||
|
|
check_desc (sd);
|
||
|
|
|
||
|
|
*reason_p = reason;
|
||
|
|
*sigrc_p = siggnal;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
sim_do_command (SIM_DESC sd, const char *cmd)
|
||
|
|
{
|
||
|
|
const char *arg;
|
||
|
|
char **argv = buildargv (cmd);
|
||
|
|
|
||
|
|
check_desc (sd);
|
||
|
|
|
||
|
|
cmd = arg = "";
|
||
|
|
if (argv != NULL)
|
||
|
|
{
|
||
|
|
if (argv[0] != NULL)
|
||
|
|
cmd = argv[0];
|
||
|
|
if (argv[1] != NULL)
|
||
|
|
arg = argv[1];
|
||
|
|
}
|
||
|
|
|
||
|
|
if (strcmp (cmd, "trace") == 0)
|
||
|
|
{
|
||
|
|
if (strcmp (arg, "on") == 0)
|
||
|
|
trace = 1;
|
||
|
|
else if (strcmp (arg, "off") == 0)
|
||
|
|
trace = 0;
|
||
|
|
else
|
||
|
|
printf ("The 'sim trace' command expects 'on' or 'off' "
|
||
|
|
"as an argument.\n");
|
||
|
|
}
|
||
|
|
else if (strcmp (cmd, "verbose") == 0)
|
||
|
|
{
|
||
|
|
if (strcmp (arg, "on") == 0)
|
||
|
|
verbose = 1;
|
||
|
|
else if (strcmp (arg, "off") == 0)
|
||
|
|
verbose = 0;
|
||
|
|
else
|
||
|
|
printf ("The 'sim verbose' command expects 'on' or 'off'"
|
||
|
|
" as an argument.\n");
|
||
|
|
}
|
||
|
|
else
|
||
|
|
printf ("The 'sim' command expects either 'trace' or 'verbose'"
|
||
|
|
" as a subcommand.\n");
|
||
|
|
|
||
|
|
freeargv (argv);
|
||
|
|
}
|
||
|
|
|
||
|
|
char **
|
||
|
|
sim_complete_command (SIM_DESC sd, const char *text, const char *word)
|
||
|
|
{
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
char *
|
||
|
|
sim_memory_map (SIM_DESC sd)
|
||
|
|
{
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
sim_info (SIM_DESC sd, int verbose)
|
||
|
|
{
|
||
|
|
printf ("The m32c minisim doesn't collect any statistics.\n");
|
||
|
|
}
|