479 lines
13 KiB
C
479 lines
13 KiB
C
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#include <stdio.h>
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#include <ctype.h>
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#include <limits.h>
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#include "ansidecl.h"
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#include "sim/callback.h"
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#include "opcode/d10v.h"
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#include "bfd.h"
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#define DEBUG_TRACE 0x00000001
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#define DEBUG_VALUES 0x00000002
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#define DEBUG_LINE_NUMBER 0x00000004
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#define DEBUG_MEMSIZE 0x00000008
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#define DEBUG_INSTRUCTION 0x00000010
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#define DEBUG_TRAP 0x00000020
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#define DEBUG_MEMORY 0x00000040
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#ifndef DEBUG
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#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
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#endif
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extern int d10v_debug;
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#include "sim/sim.h"
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#include "sim-config.h"
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#include "sim-types.h"
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/* FIXME: D10V defines */
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typedef uint16_t reg_t;
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struct simops
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{
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long opcode;
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int is_long;
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long mask;
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int format;
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int cycles;
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int unit;
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int exec_type;
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void (*func)(SIM_DESC, SIM_CPU *);
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int numops;
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int operands[9];
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};
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enum _ins_type
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{
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INS_UNKNOWN, /* unknown instruction */
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INS_COND_TRUE, /* # times EXExxx executed other instruction */
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INS_COND_FALSE, /* # times EXExxx did not execute other instruction */
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INS_COND_JUMP, /* # times JUMP skipped other instruction */
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INS_CYCLES, /* # cycles */
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INS_LONG, /* long instruction (both containers, ie FM == 11) */
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INS_LEFTRIGHT, /* # times instruction encoded as L -> R (ie, FM == 01) */
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INS_RIGHTLEFT, /* # times instruction encoded as L <- R (ie, FM == 10) */
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INS_PARALLEL, /* # times instruction encoded as L || R (ie, RM == 00) */
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INS_LEFT, /* normal left instructions */
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INS_LEFT_PARALLEL, /* left side of || */
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INS_LEFT_COND_TEST, /* EXExx test on left side */
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INS_LEFT_COND_EXE, /* execution after EXExxx test on right side succeeded */
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INS_LEFT_NOPS, /* NOP on left side */
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INS_RIGHT, /* normal right instructions */
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INS_RIGHT_PARALLEL, /* right side of || */
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INS_RIGHT_COND_TEST, /* EXExx test on right side */
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INS_RIGHT_COND_EXE, /* execution after EXExxx test on left side succeeded */
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INS_RIGHT_NOPS, /* NOP on right side */
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INS_MAX
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};
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extern unsigned long ins_type_counters[ (int)INS_MAX ];
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enum {
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SP_IDX = 15,
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};
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/* Write-back slots */
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union slot_data {
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unsigned_1 _1;
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unsigned_2 _2;
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unsigned_4 _4;
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unsigned_8 _8;
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};
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struct slot {
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void *dest;
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int size;
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union slot_data data;
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union slot_data mask;
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};
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enum {
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NR_SLOTS = 16,
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};
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#define SLOT (State.slot)
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#define SLOT_NR (State.slot_nr)
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#define SLOT_PEND_MASK(DEST, MSK, VAL) \
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do \
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{ \
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SLOT[SLOT_NR].dest = &(DEST); \
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SLOT[SLOT_NR].size = sizeof (DEST); \
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switch (sizeof (DEST)) \
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{ \
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case 1: \
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SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \
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SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \
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break; \
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case 2: \
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SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \
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SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \
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break; \
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case 4: \
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SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \
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SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \
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break; \
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case 8: \
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SLOT[SLOT_NR].data._8 = (unsigned_8) (VAL); \
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SLOT[SLOT_NR].mask._8 = (unsigned_8) (MSK); \
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break; \
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} \
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SLOT_NR = (SLOT_NR + 1); \
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} \
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while (0)
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#define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL)
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#define SLOT_DISCARD() (SLOT_NR = 0)
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#define SLOT_FLUSH() \
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do \
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{ \
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int i; \
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for (i = 0; i < SLOT_NR; i++) \
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{ \
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switch (SLOT[i].size) \
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{ \
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case 1: \
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*(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \
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*(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \
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break; \
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case 2: \
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*(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \
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*(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \
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break; \
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case 4: \
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*(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \
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*(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \
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break; \
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case 8: \
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*(unsigned_8*) SLOT[i].dest &= SLOT[i].mask._8; \
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*(unsigned_8*) SLOT[i].dest |= SLOT[i].data._8; \
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break; \
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} \
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} \
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SLOT_NR = 0; \
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} \
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while (0)
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#define SLOT_DUMP() \
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do \
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{ \
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int i; \
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for (i = 0; i < SLOT_NR; i++) \
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{ \
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switch (SLOT[i].size) \
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{ \
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case 1: \
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printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \
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(long) SLOT[i].dest, \
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(unsigned) SLOT[i].mask._1, \
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(unsigned) SLOT[i].data._1); \
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break; \
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case 2: \
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printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \
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(long) SLOT[i].dest, \
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(unsigned) SLOT[i].mask._2, \
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(unsigned) SLOT[i].data._2); \
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break; \
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case 4: \
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printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \
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(long) SLOT[i].dest, \
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(unsigned) SLOT[i].mask._4, \
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(unsigned) SLOT[i].data._4); \
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break; \
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case 8: \
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printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \
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(long) SLOT[i].dest, \
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(unsigned) (SLOT[i].mask._8 >> 32), \
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(unsigned) SLOT[i].mask._8, \
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(unsigned) (SLOT[i].data._8 >> 32), \
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(unsigned) SLOT[i].data._8); \
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break; \
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} \
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} \
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} \
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while (0)
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/* d10v memory: There are three separate d10v memory regions IMEM,
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UMEM and DMEM. The IMEM and DMEM are further broken down into
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blocks (very like VM pages). */
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enum
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{
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IMAP_BLOCK_SIZE = 0x20000,
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DMAP_BLOCK_SIZE = 0x4000,
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};
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/* Implement the three memory regions using sparse arrays. Allocate
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memory using ``segments''. A segment must be at least as large as
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a BLOCK - ensures that an access that doesn't cross a block
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boundary can't cross a segment boundary */
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enum
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{
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SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
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IMEM_SEGMENTS = 8, /* 1MB */
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DMEM_SEGMENTS = 8, /* 1MB */
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UMEM_SEGMENTS = 128 /* 16MB */
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};
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struct d10v_memory
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{
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uint8_t *insn[IMEM_SEGMENTS];
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uint8_t *data[DMEM_SEGMENTS];
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uint8_t *unif[UMEM_SEGMENTS];
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};
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struct _state
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{
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reg_t regs[16]; /* general-purpose registers */
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#define GPR(N) (State.regs[(N)] + 0)
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#define SET_GPR(N,VAL) SLOT_PEND (State.regs[(N)], (VAL))
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#define GPR32(N) ((((uint32_t) State.regs[(N) + 0]) << 16) \
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| (uint16_t) State.regs[(N) + 1])
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#define SET_GPR32(N,VAL) do { SET_GPR (OP[0] + 0, (VAL) >> 16); SET_GPR (OP[0] + 1, (VAL)); } while (0)
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reg_t cregs[16]; /* control registers */
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#define CREG(N) (State.cregs[(N)] + 0)
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#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
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#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
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reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
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#define HELD_SP(N) (State.sp[(N)] + 0)
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#define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL))
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int64_t a[2]; /* accumulators */
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#define ACC(N) (State.a[(N)] + 0)
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#define SET_ACC(N,VAL) SLOT_PEND (State.a[(N)], (VAL) & MASK40)
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/* writeback info */
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struct slot slot[NR_SLOTS];
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int slot_nr;
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/* trace data */
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struct {
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uint16_t psw;
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} trace;
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uint8_t exe;
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int pc_changed;
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/* NOTE: everything below this line is not reset by
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sim_create_inferior() */
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struct d10v_memory mem;
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enum _ins_type ins_type;
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};
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extern struct _state State;
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extern uint16_t OP[4];
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extern struct simops Simops[];
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enum
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{
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PSW_CR = 0,
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BPSW_CR = 1,
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PC_CR = 2,
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BPC_CR = 3,
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DPSW_CR = 4,
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DPC_CR = 5,
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RPT_C_CR = 7,
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RPT_S_CR = 8,
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RPT_E_CR = 9,
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MOD_S_CR = 10,
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MOD_E_CR = 11,
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IBA_CR = 14,
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};
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enum
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{
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PSW_SM_BIT = 0x8000,
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PSW_EA_BIT = 0x2000,
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PSW_DB_BIT = 0x1000,
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PSW_DM_BIT = 0x0800,
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PSW_IE_BIT = 0x0400,
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PSW_RP_BIT = 0x0200,
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PSW_MD_BIT = 0x0100,
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PSW_FX_BIT = 0x0080,
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PSW_ST_BIT = 0x0040,
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PSW_F0_BIT = 0x0008,
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PSW_F1_BIT = 0x0004,
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PSW_C_BIT = 0x0001,
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};
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#define PSW CREG (PSW_CR)
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#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
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#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
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#define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
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#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
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#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
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#define PSW_EA ((PSW & PSW_EA_BIT) != 0)
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#define SET_PSW_EA(VAL) SET_PSW_BIT (PSW_EA_BIT, (VAL))
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#define PSW_DB ((PSW & PSW_DB_BIT) != 0)
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#define SET_PSW_DB(VAL) SET_PSW_BIT (PSW_DB_BIT, (VAL))
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#define PSW_DM ((PSW & PSW_DM_BIT) != 0)
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#define SET_PSW_DM(VAL) SET_PSW_BIT (PSW_DM_BIT, (VAL))
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#define PSW_IE ((PSW & PSW_IE_BIT) != 0)
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#define SET_PSW_IE(VAL) SET_PSW_BIT (PSW_IE_BIT, (VAL))
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#define PSW_RP ((PSW & PSW_RP_BIT) != 0)
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#define SET_PSW_RP(VAL) SET_PSW_BIT (PSW_RP_BIT, (VAL))
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#define PSW_MD ((PSW & PSW_MD_BIT) != 0)
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#define SET_PSW_MD(VAL) SET_PSW_BIT (PSW_MD_BIT, (VAL))
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#define PSW_FX ((PSW & PSW_FX_BIT) != 0)
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#define SET_PSW_FX(VAL) SET_PSW_BIT (PSW_FX_BIT, (VAL))
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#define PSW_ST ((PSW & PSW_ST_BIT) != 0)
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#define SET_PSW_ST(VAL) SET_PSW_BIT (PSW_ST_BIT, (VAL))
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#define PSW_F0 ((PSW & PSW_F0_BIT) != 0)
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#define SET_PSW_F0(VAL) SET_PSW_BIT (PSW_F0_BIT, (VAL))
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#define PSW_F1 ((PSW & PSW_F1_BIT) != 0)
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#define SET_PSW_F1(VAL) SET_PSW_BIT (PSW_F1_BIT, (VAL))
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#define PSW_C ((PSW & PSW_C_BIT) != 0)
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#define SET_PSW_C(VAL) SET_PSW_BIT (PSW_C_BIT, (VAL))
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/* See simopsc.:move_to_cr() for registers that can not be read-from
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or assigned-to directly */
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#define PC CREG (PC_CR)
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#define SET_PC(VAL) SET_CREG (PC_CR, (VAL))
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||
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#define BPSW CREG (BPSW_CR)
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||
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#define SET_BPSW(VAL) SET_CREG (BPSW_CR, (VAL))
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||
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#define BPC CREG (BPC_CR)
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#define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL))
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||
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#define DPSW CREG (DPSW_CR)
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#define SET_DPSW(VAL) SET_CREG (DPSW_CR, (VAL))
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#define DPC CREG (DPC_CR)
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#define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL))
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|
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#define RPT_C CREG (RPT_C_CR)
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#define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL))
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#define RPT_S CREG (RPT_S_CR)
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#define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL))
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#define RPT_E CREG (RPT_E_CR)
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#define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL))
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#define MOD_S CREG (MOD_S_CR)
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#define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL))
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|
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||
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#define MOD_E CREG (MOD_E_CR)
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#define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL))
|
||
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|
|
||
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#define IBA CREG (IBA_CR)
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||
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#define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL))
|
||
|
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|
||
|
|
|
||
|
|
#define SIG_D10V_STOP -1
|
||
|
|
#define SIG_D10V_EXIT -2
|
||
|
|
#define SIG_D10V_BUS -3
|
||
|
|
|
||
|
|
/* TODO: Resolve conflicts with common headers. */
|
||
|
|
#undef SEXT8
|
||
|
|
#undef SEXT16
|
||
|
|
#undef SEXT32
|
||
|
|
#undef MASK32
|
||
|
|
|
||
|
|
#define SEXT3(x) ((((x)&0x7)^(~3))+4)
|
||
|
|
|
||
|
|
/* sign-extend a 4-bit number */
|
||
|
|
#define SEXT4(x) ((((x)&0xf)^(~7))+8)
|
||
|
|
|
||
|
|
/* sign-extend an 8-bit number */
|
||
|
|
#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
|
||
|
|
|
||
|
|
/* sign-extend a 16-bit number */
|
||
|
|
#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
|
||
|
|
|
||
|
|
/* sign-extend a 32-bit number */
|
||
|
|
#define SEXT32(x) ((((x)&SIGNED64(0xffffffff))^(~SIGNED64(0x7fffffff)))+SIGNED64(0x80000000))
|
||
|
|
|
||
|
|
/* sign extend a 40 bit number */
|
||
|
|
#define SEXT40(x) ((((x)&SIGNED64(0xffffffffff))^(~SIGNED64(0x7fffffffff)))+SIGNED64(0x8000000000))
|
||
|
|
|
||
|
|
/* sign extend a 44 bit number */
|
||
|
|
#define SEXT44(x) ((((x)&SIGNED64(0xfffffffffff))^(~SIGNED64(0x7ffffffffff)))+SIGNED64(0x80000000000))
|
||
|
|
|
||
|
|
/* sign extend a 56 bit number */
|
||
|
|
#define SEXT56(x) ((((x)&SIGNED64(0xffffffffffffff))^(~SIGNED64(0x7fffffffffffff)))+SIGNED64(0x80000000000000))
|
||
|
|
|
||
|
|
/* sign extend a 60 bit number */
|
||
|
|
#define SEXT60(x) ((((x)&SIGNED64(0xfffffffffffffff))^(~SIGNED64(0x7ffffffffffffff)))+SIGNED64(0x800000000000000))
|
||
|
|
|
||
|
|
#define MAX32 SIGNED64(0x7fffffff)
|
||
|
|
#define MIN32 SIGNED64(0xff80000000)
|
||
|
|
#define MASK32 SIGNED64(0xffffffff)
|
||
|
|
#define MASK40 SIGNED64(0xffffffffff)
|
||
|
|
|
||
|
|
/* The alignment of MOD_E in the following macro depends upon "i"
|
||
|
|
always being a power of 2. */
|
||
|
|
#define INC_ADDR(x,i) \
|
||
|
|
do \
|
||
|
|
{ \
|
||
|
|
int test_i = i < 0 ? i : ~((i) - 1); \
|
||
|
|
if (PSW_MD && GPR (x) == (MOD_E & test_i)) \
|
||
|
|
SET_GPR (x, MOD_S & test_i); \
|
||
|
|
else \
|
||
|
|
SET_GPR (x, GPR (x) + (i)); \
|
||
|
|
} \
|
||
|
|
while (0)
|
||
|
|
|
||
|
|
extern uint8_t *dmem_addr (SIM_DESC, SIM_CPU *, uint16_t offset);
|
||
|
|
extern uint8_t *imem_addr (SIM_DESC, SIM_CPU *, uint32_t);
|
||
|
|
|
||
|
|
#define RB(x) (*(dmem_addr (sd, cpu, x)))
|
||
|
|
#define SB(addr,data) ( RB(addr) = (data & 0xff))
|
||
|
|
|
||
|
|
#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
|
||
|
|
#define ENDIAN_INLINE static __inline__
|
||
|
|
#include "endian.c"
|
||
|
|
#undef ENDIAN_INLINE
|
||
|
|
|
||
|
|
#else
|
||
|
|
extern uint32_t get_longword (uint8_t *);
|
||
|
|
extern uint16_t get_word (uint8_t *);
|
||
|
|
extern int64_t get_longlong (uint8_t *);
|
||
|
|
extern void write_word (uint8_t *addr, uint16_t data);
|
||
|
|
extern void write_longword (uint8_t *addr, uint32_t data);
|
||
|
|
extern void write_longlong (uint8_t *addr, int64_t data);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
|
||
|
|
#define RW(x) get_word (dmem_addr (sd, cpu, x))
|
||
|
|
#define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data)
|
||
|
|
#define RLW(x) get_longword (dmem_addr (sd, cpu, x))
|
||
|
|
#define READ_16(x) get_word(x)
|
||
|
|
#define WRITE_16(addr,data) write_word(addr,data)
|
||
|
|
#define READ_64(x) get_longlong(x)
|
||
|
|
#define WRITE_64(addr,data) write_longlong(addr,data)
|
||
|
|
|
||
|
|
#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
|
||
|
|
|
||
|
|
#define RIE_VECTOR_START 0xffc2
|
||
|
|
#define AE_VECTOR_START 0xffc3
|
||
|
|
#define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */
|
||
|
|
#define DBT_VECTOR_START 0xffd4
|
||
|
|
#define SDBT_VECTOR_START 0xffd5
|
||
|
|
|
||
|
|
/* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
|
||
|
|
cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
|
||
|
|
(VAL & ~MASK)). In addition, unless PSW_HW_P, a VAL intended for
|
||
|
|
PSW is masked for zero bits. */
|
||
|
|
|
||
|
|
extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);
|