204 lines
6.3 KiB
C
204 lines
6.3 KiB
C
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/* Copyright (C) 2021 Free Software Foundation, Inc.
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Contributed by Oracle.
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This file is part of GNU Binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#if defined(__i386__) || defined(__x86_64)
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#include <cpuid.h> /* GCC-provided */
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#elif defined(__aarch64__)
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#define ATTRIBUTE_UNUSED __attribute__((unused))
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static inline uint_t __attribute_const__
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__get_cpuid (unsigned int op ATTRIBUTE_UNUSED, unsigned int *eax,
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unsigned int *ebx ATTRIBUTE_UNUSED,
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unsigned int *ecx ATTRIBUTE_UNUSED, unsigned int *edx ATTRIBUTE_UNUSED)
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{
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// CPUID bit assignments:
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// [31:24] IMPLEMENTER (0x50 - ARM_CPU_IMP_APM)
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// [23:20] VARIANT indicates processor revision (0x2 = Revision 2)
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// [19:16] Constant (Reads as 0xF)
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// [15:04] PARTNO indicates part number (0xC23 = Cortex-M3)
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// [03:00] REVISION indicates patch release (0x0 = Patch 0)
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// unsigned long v = 0;
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// __asm volatile ("MRS %[result], MPIDR_EL1" : [result] "=r" (v));
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// Tprintf(DBG_LT0, "cpuid.c:%d read_cpuid_id() MPIDR_EL1=0x%016lx\n", __LINE__, v);
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uint_t res = 0;
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__asm volatile ("MRS %[result], MIDR_EL1" : [result] "=r" (*eax));
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Tprintf (DBG_LT0, "cpuid.c:%d read_cpuid_id() MIDR_EL1=0x%016x\n", __LINE__, *eax);
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return res;
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}
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#endif
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/*
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* Various routines to handle identification
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* and classification of x86 processors.
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*/
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#define IS_GLOBAL /* externally visible */
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#define X86_VENDOR_Intel 0
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#define X86_VENDORSTR_Intel "GenuineIntel"
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#define X86_VENDOR_IntelClone 1
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#define X86_VENDOR_AMD 2
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#define X86_VENDORSTR_AMD "AuthenticAMD"
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#define BITX(u, h, l) (((u) >> (l)) & ((1LU << ((h) - (l) + 1LU)) - 1LU))
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#define CPI_FAMILY_XTD(reg) BITX(reg, 27, 20)
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#define CPI_MODEL_XTD(reg) BITX(reg, 19, 16)
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#define CPI_TYPE(reg) BITX(reg, 13, 12)
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#define CPI_FAMILY(reg) BITX(reg, 11, 8)
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#define CPI_STEP(reg) BITX(reg, 3, 0)
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#define CPI_MODEL(reg) BITX(reg, 7, 4)
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#define IS_EXTENDED_MODEL_INTEL(model) ((model) == 0x6 || (model) >= 0xf)
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typedef struct
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{
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unsigned int eax;
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unsigned int ebx;
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unsigned int ecx;
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unsigned int edx;
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} cpuid_regs_t;
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typedef struct
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{
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unsigned int cpi_model;
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unsigned int cpi_family;
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unsigned int cpi_vendor; /* enum of cpi_vendorstr */
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unsigned int cpi_maxeax; /* fn 0: %eax */
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char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */
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} cpuid_info_t;
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#if defined(__i386__) || defined(__x86_64)
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static uint_t
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cpuid_vendorstr_to_vendorcode (char *vendorstr)
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{
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if (strcmp (vendorstr, X86_VENDORSTR_Intel) == 0)
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return X86_VENDOR_Intel;
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else if (strcmp (vendorstr, X86_VENDORSTR_AMD) == 0)
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return X86_VENDOR_AMD;
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else
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return X86_VENDOR_IntelClone;
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}
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static int
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my_cpuid (unsigned int op, cpuid_regs_t *regs)
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{
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regs->eax = regs->ebx = regs->ecx = regs->edx = 0;
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int ret = __get_cpuid (op, ®s->eax, ®s->ebx, ®s->ecx, ®s->edx);
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TprintfT (DBG_LT1, "my_cpuid: __get_cpuid(0x%x, 0x%x, 0x%x, 0x%x, 0x%x) returns %d\n",
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op, regs->eax, regs->ebx, regs->ecx, regs->edx, ret);
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return ret;
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}
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#endif
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static cpuid_info_t *
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get_cpuid_info ()
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{
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static int cpuid_inited = 0;
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static cpuid_info_t cpuid_info;
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cpuid_info_t *cpi = &cpuid_info;
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if (cpuid_inited)
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return cpi;
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cpuid_inited = 1;
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#if defined(__aarch64__)
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// CPUID bit assignments:
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// [31:24] IMPLEMENTER (0x50 - ARM_CPU_IMP_APM)
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// [23:20] VARIANT indicates processor revision (0x2 = Revision 2)
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// [19:16] Constant (Reads as 0xF)
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// [15:04] PARTNO indicates part number (0xC23 = Cortex-M3)
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// [03:00] REVISION indicates patch release (0x0 = Patch 0)
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uint_t reg = 0;
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__asm volatile ("MRS %[result], MIDR_EL1" : [result] "=r" (reg));
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cpi->cpi_vendor = reg >> 24;
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cpi->cpi_model = (reg >> 4) & 0xfff;
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switch (cpi->cpi_vendor)
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{
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case ARM_CPU_IMP_APM:
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case ARM_CPU_IMP_ARM:
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case ARM_CPU_IMP_CAVIUM:
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case ARM_CPU_IMP_BRCM:
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case ARM_CPU_IMP_QCOM:
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strncpy (cpi->cpi_vendorstr, AARCH64_VENDORSTR_ARM, sizeof (cpi->cpi_vendorstr));
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break;
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default:
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strncpy (cpi->cpi_vendorstr, "UNKNOWN ARM", sizeof (cpi->cpi_vendorstr));
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break;
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}
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Tprintf (DBG_LT0, "cpuid.c:%d read_cpuid_id() MIDR_EL1==0x%016x cpi_vendor=%d cpi_model=%d\n",
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__LINE__, (unsigned int) reg, cpi->cpi_vendor, cpi->cpi_model);
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#elif defined(__i386__) || defined(__x86_64)
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cpuid_regs_t regs;
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my_cpuid (0, ®s);
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cpi->cpi_maxeax = regs.eax;
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((uint32_t *) cpi->cpi_vendorstr)[0] = regs.ebx;
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((uint32_t *) cpi->cpi_vendorstr)[1] = regs.edx;
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((uint32_t *) cpi->cpi_vendorstr)[2] = regs.ecx;
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cpi->cpi_vendorstr[12] = 0;
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cpi->cpi_vendor = cpuid_vendorstr_to_vendorcode (cpi->cpi_vendorstr);
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my_cpuid (1, ®s);
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cpi->cpi_model = CPI_MODEL (regs.eax);
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cpi->cpi_family = CPI_FAMILY (regs.eax);
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if (cpi->cpi_family == 0xf)
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cpi->cpi_family += CPI_FAMILY_XTD (regs.eax);
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/*
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* Beware: AMD uses "extended model" iff base *FAMILY* == 0xf.
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* Intel, and presumably everyone else, uses model == 0xf, as
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* one would expect (max value means possible overflow). Sigh.
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*/
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switch (cpi->cpi_vendor)
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{
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case X86_VENDOR_Intel:
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if (IS_EXTENDED_MODEL_INTEL (cpi->cpi_family))
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cpi->cpi_model += CPI_MODEL_XTD (regs.eax) << 4;
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break;
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case X86_VENDOR_AMD:
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if (CPI_FAMILY (cpi->cpi_family) == 0xf)
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cpi->cpi_model += CPI_MODEL_XTD (regs.eax) << 4;
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break;
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default:
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if (cpi->cpi_model == 0xf)
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cpi->cpi_model += CPI_MODEL_XTD (regs.eax) << 4;
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break;
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}
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#endif
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return cpi;
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}
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static inline uint_t
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cpuid_getvendor ()
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{
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return get_cpuid_info ()->cpi_vendor;
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}
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static inline uint_t
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cpuid_getfamily ()
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{
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return get_cpuid_info ()->cpi_family;
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}
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static inline uint_t
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cpuid_getmodel ()
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{
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return get_cpuid_info ()->cpi_model;
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}
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