83 lines
4.3 KiB
Text
83 lines
4.3 KiB
Text
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<<<
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:sectnums:
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==== True Random-Number Generator (TRNG)
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[cols="<3,<3,<4"]
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[frame="topbot",grid="none"]
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|=======================
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| Hardware source file(s): | neorv32_trng.vhd |
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| Software driver file(s): | neorv32_trng.c |
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| | neorv32_trng.h |
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| Top entity port: | none |
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| Configuration generics: | _IO_TRNG_EN_ | implement TRNG when _true_
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| | _IO_TRNG_FIFO_ | data FIFO depth, min 1, has to be a power of two
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| CPU interrupts: | none |
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|=======================
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**Theory of Operation**
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The NEORV32 true random number generator provides _physically_ true random numbers.
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Instead of using a pseudo RNG like a LFSR, the TRNG uses a simple, straight-forward ring
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oscillator concept as physical entropy source. Hence, voltage, thermal and also semiconductor manufacturing
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fluctuations are used to provide a true physical entropy source.
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The TRNG features a platform independent architecture without FPGA-specific primitives, macros or
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attributes so it can be synthesized for _any_ FPGA. Ir is based on the **neoTRNG V2**, which is a "spin-off project" of the
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NEORV32 processor. More detailed information about the neoTRNG, its architecture and a
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detailed evaluation of the random number quality can be found it the neoTRNG repository: https://github.com/stnolting/neoTRNG
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.Inferring Latches
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[NOTE]
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The synthesis tool might emit a warning like _"inferring latches for ... neorv32_trng ..."_. This is no problem
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as this is what we actually want: the TRNG is based on latches, which implement the inverters of the ring oscillators.
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.Simulation
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[IMPORTANT]
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When simulating the processor the NEORV32 TRNG is automatically set to "simulation mode". In this mode, the physical entropy
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sources (= the ring oscillators) are replaced by a simple **pseudo RNG (LFSR)** providing weak pseudo-random data only.
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The _TRNG_CTRL_SIM_MODE_ flag of the control register is set if simulation mode is active.
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**Using the TRNG**
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The TRNG features a single control register `CTRL` for control, status check and data access. When the _TRNG_CTRL_EN_
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bit is set, the TRNG is enabled and starts operation.
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.TRNG Reset
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[NOTE]
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The TRNG core does not provide a dedicated reset. In order to ensure correct operations, the TRNG should be
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disabled (=reset) by clearing the _TRNG_CTRL_EN_ and waiting some 1000s clock cycles before re-enabling it.
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As soon as the _TRNG_CTRL_VALID_ bit is set a new random data byte is available and can be obtained from the lowest 8 bits
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of the `CTRL` register (_TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_LSB_). If this bit is cleared, there is no valid data available
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and the lowest 8 bit of the `CTRL` register are set to all-zero.
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.Read Access Security
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[NOTE]
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The random data byte (_TRNG_CTRL_DATA_) in the control register is automatically cleared after each read access
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to prevent software from reading the _same_ random data byte more than once.
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An optional random data FIFO can be configured using the <<_io_trng_fifo>> generic. This FIFO automatically samples
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new random data from the TRNG to provide some kind of _random data pool_ for applications, which require a large number
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of RND data in a short time. The minimal and default value for <<_io_trng_fifo>> is 1 (implementing a register rather
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than a real FIFO); the generic has to be a power of two.
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The random data FIFO can be cleared at any time either by disabling the TRNG via the _TRNG_CTRL_EN_ flag or by
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setting the _TRNG_CTRL_FIFO_CLR_ flag. Note that this flag is write-only and auto clears after being set.
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**Register Map**
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.TRNG register map (`struct NEORV32_TRNG`)
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.5+<| `0xffffffb8` .5+<| `NEORV32_TRNG.CTRL` <|`7:0` _TRNG_CTRL_DATA_MSB_ : _TRNG_CTRL_DATA_MSB_ ^| r/- <| 8-bit random data
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<|`28` _TRNG_CTRL_FIFO_CLR_ ^| -/w <| flush random data FIFO when set (auto clears)
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<|`29` _TRNG_CTRL_SIM_MODE_ ^| r/- <| simulation mode (PRNG!)
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<|`30` _TRNG_CTRL_EN_ ^| r/w <| TRNG enable
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<|`31` _TRNG_CTRL_VALID_ ^| r/- <| random data is valid when set
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|=======================
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