411 lines
11 KiB
C
411 lines
11 KiB
C
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/*
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* OpenRISC virtual CPU header.
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*
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* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef OPENRISC_CPU_H
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#define OPENRISC_CPU_H
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#include "exec/cpu-defs.h"
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#include "fpu/softfloat-types.h"
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#include "hw/core/cpu.h"
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#include "qom/object.h"
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#define TYPE_OPENRISC_CPU "or1k-cpu"
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OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
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/**
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* OpenRISCCPUClass:
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* @parent_realize: The parent class' realize handler.
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* @parent_reset: The parent class' reset handler.
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*
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* A OpenRISC CPU model.
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*/
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struct OpenRISCCPUClass {
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/*< private >*/
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CPUClass parent_class;
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/*< public >*/
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DeviceRealize parent_realize;
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DeviceReset parent_reset;
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};
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#define TARGET_INSN_START_EXTRA_WORDS 1
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enum {
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MMU_NOMMU_IDX = 0,
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MMU_SUPERVISOR_IDX = 1,
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MMU_USER_IDX = 2,
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};
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#define SET_FP_CAUSE(reg, v) do {\
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(reg) = ((reg) & ~(0x3f << 12)) | \
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((v & 0x3f) << 12);\
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} while (0)
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#define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
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#define UPDATE_FP_FLAGS(reg, v) do {\
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(reg) |= ((v & 0x1f) << 2);\
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} while (0)
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/* Interrupt */
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#define NR_IRQS 32
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/* Unit presece register */
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enum {
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UPR_UP = (1 << 0),
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UPR_DCP = (1 << 1),
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UPR_ICP = (1 << 2),
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UPR_DMP = (1 << 3),
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UPR_IMP = (1 << 4),
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UPR_MP = (1 << 5),
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UPR_DUP = (1 << 6),
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UPR_PCUR = (1 << 7),
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UPR_PMP = (1 << 8),
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UPR_PICP = (1 << 9),
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UPR_TTP = (1 << 10),
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UPR_CUP = (255 << 24),
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};
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/* CPU configure register */
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enum {
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CPUCFGR_NSGF = (15 << 0),
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CPUCFGR_CGF = (1 << 4),
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CPUCFGR_OB32S = (1 << 5),
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CPUCFGR_OB64S = (1 << 6),
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CPUCFGR_OF32S = (1 << 7),
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CPUCFGR_OF64S = (1 << 8),
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CPUCFGR_OV64S = (1 << 9),
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CPUCFGR_ND = (1 << 10),
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CPUCFGR_AVRP = (1 << 11),
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CPUCFGR_EVBARP = (1 << 12),
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CPUCFGR_ISRP = (1 << 13),
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CPUCFGR_AECSRP = (1 << 14),
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CPUCFGR_OF64A32S = (1 << 15),
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};
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/* DMMU configure register */
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enum {
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DMMUCFGR_NTW = (3 << 0),
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DMMUCFGR_NTS = (7 << 2),
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DMMUCFGR_NAE = (7 << 5),
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DMMUCFGR_CRI = (1 << 8),
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DMMUCFGR_PRI = (1 << 9),
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DMMUCFGR_TEIRI = (1 << 10),
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DMMUCFGR_HTR = (1 << 11),
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};
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/* IMMU configure register */
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enum {
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IMMUCFGR_NTW = (3 << 0),
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IMMUCFGR_NTS = (7 << 2),
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IMMUCFGR_NAE = (7 << 5),
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IMMUCFGR_CRI = (1 << 8),
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IMMUCFGR_PRI = (1 << 9),
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IMMUCFGR_TEIRI = (1 << 10),
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IMMUCFGR_HTR = (1 << 11),
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};
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/* Power management register */
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enum {
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PMR_SDF = (15 << 0),
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PMR_DME = (1 << 4),
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PMR_SME = (1 << 5),
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PMR_DCGE = (1 << 6),
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PMR_SUME = (1 << 7),
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};
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/* Float point control status register */
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enum {
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FPCSR_FPEE = 1,
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FPCSR_RM = (3 << 1),
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FPCSR_OVF = (1 << 3),
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FPCSR_UNF = (1 << 4),
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FPCSR_SNF = (1 << 5),
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FPCSR_QNF = (1 << 6),
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FPCSR_ZF = (1 << 7),
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FPCSR_IXF = (1 << 8),
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FPCSR_IVF = (1 << 9),
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FPCSR_INF = (1 << 10),
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FPCSR_DZF = (1 << 11),
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};
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/* Exceptions indices */
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enum {
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EXCP_RESET = 0x1,
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EXCP_BUSERR = 0x2,
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EXCP_DPF = 0x3,
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EXCP_IPF = 0x4,
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EXCP_TICK = 0x5,
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EXCP_ALIGN = 0x6,
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EXCP_ILLEGAL = 0x7,
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EXCP_INT = 0x8,
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EXCP_DTLBMISS = 0x9,
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EXCP_ITLBMISS = 0xa,
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EXCP_RANGE = 0xb,
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EXCP_SYSCALL = 0xc,
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EXCP_FPE = 0xd,
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EXCP_TRAP = 0xe,
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EXCP_NR,
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};
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/* Supervisor register */
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enum {
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SR_SM = (1 << 0),
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SR_TEE = (1 << 1),
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SR_IEE = (1 << 2),
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SR_DCE = (1 << 3),
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SR_ICE = (1 << 4),
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SR_DME = (1 << 5),
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SR_IME = (1 << 6),
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SR_LEE = (1 << 7),
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SR_CE = (1 << 8),
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SR_F = (1 << 9),
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SR_CY = (1 << 10),
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SR_OV = (1 << 11),
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SR_OVE = (1 << 12),
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SR_DSX = (1 << 13),
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SR_EPH = (1 << 14),
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SR_FO = (1 << 15),
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SR_SUMRA = (1 << 16),
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SR_SCE = (1 << 17),
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};
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/* Tick Timer Mode Register */
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enum {
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TTMR_TP = (0xfffffff),
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TTMR_IP = (1 << 28),
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TTMR_IE = (1 << 29),
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TTMR_M = (3 << 30),
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};
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/* Timer Mode */
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enum {
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TIMER_NONE = (0 << 30),
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TIMER_INTR = (1 << 30),
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TIMER_SHOT = (2 << 30),
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TIMER_CONT = (3 << 30),
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};
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/* TLB size */
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enum {
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TLB_SIZE = 128,
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TLB_MASK = TLB_SIZE - 1,
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};
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/* TLB prot */
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enum {
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URE = (1 << 6),
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UWE = (1 << 7),
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SRE = (1 << 8),
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SWE = (1 << 9),
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SXE = (1 << 6),
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UXE = (1 << 7),
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};
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typedef struct OpenRISCTLBEntry {
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uint32_t mr;
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uint32_t tr;
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} OpenRISCTLBEntry;
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#ifndef CONFIG_USER_ONLY
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typedef struct CPUOpenRISCTLBContext {
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OpenRISCTLBEntry itlb[TLB_SIZE];
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OpenRISCTLBEntry dtlb[TLB_SIZE];
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int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot,
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target_ulong address, int rw);
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int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu,
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hwaddr *physical,
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int *prot,
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target_ulong address, int rw);
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} CPUOpenRISCTLBContext;
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#endif
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typedef struct CPUArchState {
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target_ulong shadow_gpr[16][32]; /* Shadow registers */
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target_ulong pc; /* Program counter */
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target_ulong ppc; /* Prev PC */
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target_ulong jmp_pc; /* Jump PC */
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uint64_t mac; /* Multiply registers MACHI:MACLO */
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target_ulong epcr; /* Exception PC register */
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target_ulong eear; /* Exception EA register */
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target_ulong sr_f; /* the SR_F bit, values 0, 1. */
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target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
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target_long sr_ov; /* the SR_OV bit (in the sign bit only) */
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uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
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uint32_t esr; /* Exception supervisor register */
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uint32_t evbar; /* Exception vector base address register */
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uint32_t pmr; /* Power Management Register */
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uint32_t fpcsr; /* Float register */
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float_status fp_status;
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target_ulong lock_addr;
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target_ulong lock_value;
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uint32_t dflag; /* In delay slot (boolean) */
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#ifndef CONFIG_USER_ONLY
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CPUOpenRISCTLBContext tlb;
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#endif
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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/* Fields from here on are preserved across CPU reset. */
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uint32_t vr; /* Version register */
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uint32_t vr2; /* Version register 2 */
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uint32_t avr; /* Architecture version register */
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uint32_t upr; /* Unit presence register */
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uint32_t cpucfgr; /* CPU configure register */
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uint32_t dmmucfgr; /* DMMU configure register */
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uint32_t immucfgr; /* IMMU configure register */
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#ifndef CONFIG_USER_ONLY
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QEMUTimer *timer;
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uint32_t ttmr; /* Timer tick mode register */
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int is_counting;
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uint32_t picmr; /* Interrupt mask register */
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uint32_t picsr; /* Interrupt contrl register*/
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#endif
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} CPUOpenRISCState;
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/**
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* OpenRISCCPU:
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* @env: #CPUOpenRISCState
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*
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* A OpenRISC CPU.
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*/
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struct ArchCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUOpenRISCState env;
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};
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void cpu_openrisc_list(void);
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void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void openrisc_translate_init(void);
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int print_insn_or1k(bfd_vma addr, disassemble_info *info);
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#define cpu_list cpu_openrisc_list
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#ifndef CONFIG_USER_ONLY
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bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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extern const VMStateDescription vmstate_openrisc_cpu;
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void openrisc_cpu_do_interrupt(CPUState *cpu);
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bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
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/* hw/openrisc_pic.c */
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void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
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/* hw/openrisc_timer.c */
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void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
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uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu);
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void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val);
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void cpu_openrisc_count_update(OpenRISCCPU *cpu);
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void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
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void cpu_openrisc_count_start(OpenRISCCPU *cpu);
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void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
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#endif
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#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
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#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX
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#define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU
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#include "exec/cpu-all.h"
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#define TB_FLAGS_SM SR_SM
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#define TB_FLAGS_DME SR_DME
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#define TB_FLAGS_IME SR_IME
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#define TB_FLAGS_OVE SR_OVE
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#define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */
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#define TB_FLAGS_R0_0 4 /* reuse SR_IEE */
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static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i)
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{
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return env->shadow_gpr[0][i];
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}
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static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
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{
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env->shadow_gpr[0][i] = val;
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|
|
}
|
||
|
|
|
||
|
|
static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
|
||
|
|
target_ulong *pc,
|
||
|
|
target_ulong *cs_base, uint32_t *flags)
|
||
|
|
{
|
||
|
|
*pc = env->pc;
|
||
|
|
*cs_base = 0;
|
||
|
|
*flags = (env->dflag ? TB_FLAGS_DFLAG : 0)
|
||
|
|
| (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
|
||
|
|
| (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
|
||
|
|
{
|
||
|
|
int ret = MMU_NOMMU_IDX; /* mmu is disabled */
|
||
|
|
|
||
|
|
if (env->sr & (ifetch ? SR_IME : SR_DME)) {
|
||
|
|
/* The mmu is enabled; test supervisor state. */
|
||
|
|
ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
|
||
|
|
{
|
||
|
|
return (env->sr
|
||
|
|
+ env->sr_f * SR_F
|
||
|
|
+ env->sr_cy * SR_CY
|
||
|
|
+ (env->sr_ov < 0) * SR_OV);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val)
|
||
|
|
{
|
||
|
|
env->sr_f = (val & SR_F) != 0;
|
||
|
|
env->sr_cy = (val & SR_CY) != 0;
|
||
|
|
env->sr_ov = (val & SR_OV ? -1 : 0);
|
||
|
|
env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO;
|
||
|
|
}
|
||
|
|
|
||
|
|
void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val);
|
||
|
|
|
||
|
|
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
|
||
|
|
|
||
|
|
#endif /* OPENRISC_CPU_H */
|